[S] Change in coreboot[master]: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes

[Mario Scheithauer (Code Review)]

Attention is currently required from: Mario Scheithauer.

Hello build bot (Jenkins), Werner Zeh, Jan Samek,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/74650

to look at the new patch set (#4).

Change subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes
......................................................................

mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes

Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).

Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig
1 file changed, 16 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/74650/4