[L] Change in coreboot[main]: mb/hardkernel/odroid-h4: Add initial ODROID-H4 series support

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Alicja Michalska, Angel Pons, David Milosevic, Felix Singer.

Lean Sheng Tan has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )

Change subject: mb/hardkernel/odroid-h4: Add initial ODROID-H4 series support
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Patch Set 6:

(2 comments)

File src/mainboard/hardkernel/odroid-h4/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/83979/comment/86db0d71_1c199c41?usp... :
PS2, Line 82: #device ref pcie_rp3 on
            : 		#	register "pch_pcie_rp[PCH_RP(3)]" = "{
            : 		#		.clk_src = 2,
            : 		#		.clk_req = 2,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#	smbios_slot_desc	"SlotTypeM2Socket3" "SlotLengthOther"
            : 		#				"M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X"
            : 		#end
            : 		#device ref pcie_rp7 on	# LAN1
            : 		#	register "pch_pcie_rp[PCH_RP(7)]" = "{
            : 		#		.clk_src = 3,
            : 		#		.clk_req = 3,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#end
            : 		#device ref pcie_rp9 on	# LAN2
            : 		#	register "pch_pcie_rp[PCH_RP(9)]" = "{
            : 		#		.clk_src = 0,
            : 		#		.clk_req = 0,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#end
            : 		#device ref pcie_rp10 on
            : 		#	register "pch_pcie_rp[PCH_RP(10)]" = "{
            : 		#		.clk_src = 1,
            : 		#		.clk_req = 1,
            : 		#		.flags = PCIE_RP_CLK_REQ_DETECT,
            : 		#	}"
            : 		#	smbios_slot_desc	"SlotTypeM2Socket1_SD" "SlotLengthOther"
            : 		#				"M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X"
            : 		#end
> The only meaningful difference I see is that you've disabled ASPM, which can help if the CLKREQ stuf […]

Done

https://review.coreboot.org/c/coreboot/+/83979/comment/66387361_81c68150?usp... :
PS2, Line 151: 	device ref uart0 on
             : 			register "serial_io_uart_mode" = "{
             : 				[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
             : 			}"
             : 		end
> I can't see this being used in the schematics, the UART on the 2x12 header comes from the IT8613E Su […]

Done