Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31888 )
Change subject: soc/intel/cannonlake: Ignore GBE LTR
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variants...
File src/mainboard/google/sarien/variants/sarien/ramstage.c:
https://review.coreboot.org/#/c/31888/4/src/mainboard/google/sarien/variants...
PS4, Line 29: ignore_gbe_ltr
Could this be done at the SOC level based on whether LAN+s0ix is enabled?
I think that's generic consideration for GBE low power consideration even without s0ix.
--
To view, visit
https://review.coreboot.org/c/coreboot/+/31888
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iec7dd197b8a456751f8e4dcb19e3e153f5888613
Gerrit-Change-Number: 31888
Gerrit-PatchSet: 4
Gerrit-Owner: Lijian Zhao
lijian.zhao@intel.com
Gerrit-Reviewer: Duncan Laurie
dlaurie@chromium.org
Gerrit-Reviewer: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Lijian Zhao
lijian.zhao@intel.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Roy Mingi Park
roy.mingi.park@intel.com
Gerrit-Reviewer: Roy Park
roy.mingi.park@intel.corp-partner.google.com
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 28 Mar 2019 19:14:37 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Duncan Laurie
dlaurie@chromium.org
Gerrit-MessageType: comment