Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61431 )
Change subject: soc/intel/common/cse: Rework `heci_disable` function ......................................................................
soc/intel/common/cse: Rework `heci_disable` function
This patch provides the possible options for SoC users to choose the applicable interface to make HECI1 function disable at pre-boot.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI` config is used for disabling heci1 using non-posted sideband write (inside SMM) after FSP-S sets the postboot_sai attribute. Applicable from CNL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC` config is used for disabling heci1 using PMC IPC command `0xA9`. Applicable from TGL PCH onwards.
`SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR` config is used for disabling heci1 using private configuration register (PCR) write. Applicable for SoC platform prior to CNL PCH.
BUG=none TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I7e0bab0004013b999ec1e054310763427d7b9348 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc M src/soc/intel/common/block/cse/disable_heci.c M src/soc/intel/common/block/include/intelblocks/cse.h 4 files changed, 63 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/61431/1
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 23e08e6..cc1c93e 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -14,13 +14,34 @@ Mainboard users to select this config to make HECI1 `function disable` prior to handing off to payload.
-config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM +config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI bool default y if HECI_DISABLE_USING_SMM select SOC_INTEL_COMMON_BLOCK_P2SB help - Use this config to include common CSE block to make HECI function - disable in SMM mode + From CNL PCH onwards,`HECI1` disabling can only done using + non-posted sideband write after FSP-S sets the postboot_sai + attribute. + Use this config to include common CSE block to make + HECI function disable in SMM mode + +config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC + bool + default n + select SOC_INTEL_COMMON_BLOCK_PMC + help + From TGL PCH onwards, an alternative mechanism developed for + disabling `HECI1`device using PMC IPC command `0xA9`. + Allowing disabling heci1 device using PMC IPC doesn't required + to run the operation in SMM. + +config SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR + bool + default n + select SOC_INTEL_COMMON_BLOCK_PCR + help + Prior to postboot_sai enforcement since CNL PCH, `HECI1` device were + disable using private configuration register (PCR) write.
config SOC_INTEL_CSE_LITE_SKU bool diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 0e5dcda..c94f8fab 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,8 +1,8 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c disable_heci.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c -smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c
ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c
diff --git a/src/soc/intel/common/block/cse/disable_heci.c b/src/soc/intel/common/block/cse/disable_heci.c index 1256fd1..14d5cd1 100644 --- a/src/soc/intel/common/block/cse/disable_heci.c +++ b/src/soc/intel/common/block/cse/disable_heci.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#define __SIMPLE_DEVICE__ + #include <commonlib/helpers.h> #include <console/console.h> #include <device/pci.h> @@ -15,8 +17,20 @@ #define CSME0_BAR 0x0 #define CSME0_FID 0xb0
+/* Disable HECI using PCR */ +static void heci_disable_using_pcr(void) +{ + soc_disable_heci_using_pcr(); +} + +/* Disable HECI using PMC IPC communication */ +static void heci_disable_using_pmc(void) +{ + cse_disable_mei_devices(); +} + /* Disable HECI using Sideband interface communication */ -void heci_disable(void) +static void heci_disable_using_sbi(void) { struct pcr_sbi_msg msg = { .pid = PID_CSME0, @@ -46,3 +60,18 @@ /* hide p2sb device */ p2sb_hide(); } + +void heci_disable(void) +{ + if (!CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + return; + + if (ENV_SMM && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_SBI)) + return heci_disable_using_sbi(); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PMC_IPC)) + return heci_disable_using_pmc(); + else if (CONFIG(SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_USING_PCR)) + return heci_disable_using_pcr(); + else + printk(BIOS_ERR, "%s Fail to make HECI function disable\n", __func__); +} diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 9bf35da..3fa29d1 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -489,4 +489,11 @@ /* Function to make cse disable using PMC IPC */ bool cse_disable_mei_devices(void);
+/* + * SoC override API to make cse disable using PCR + * PSF port id for disabling cse is expected to be different between + * SoC generation hence, allow SoC to implement the override. + */ +void soc_disable_heci_using_pcr(void); + #endif // SOC_INTEL_COMMON_CSE_H