New patch to review for coreboot: 166aab6 ipq806x: Add generic support skeleton for ipq806x
Isaac Christensen (isaac.christensen@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6963
-gerrit
commit 166aab60c37bacf4827df467ed212f2297ace795 Author: Furquan Shaikh furquan@google.com Date: Wed Mar 19 14:29:48 2014 -0700
ipq806x: Add generic support skeleton for ipq806x
Skeleton for soc ipq806x
Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury vbendeb@chromium.org Commit-Queue: Furquan Shaikh furquan@chromium.org Tested-by: Furquan Shaikh furquan@chromium.org (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911)
soc/ipq806x: Disable LPAE mode.
LPAE (large physical address extension) is not available on this SOC core, do not enable it.
Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani deepad@codeaurora.com Signed-off-by: Vadim Bendebury vbendeb@chromium.org Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani deepad@quicinc.com (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b)
Squashed 2 commits for the Qualcomm ipq806x SOC.
Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen isaac.christensen@se-eng.com --- src/soc/Kconfig | 3 ++- src/soc/Makefile.inc | 1 + src/soc/qualcomm/Kconfig | 1 + src/soc/qualcomm/Makefile.inc | 1 + src/soc/qualcomm/ipq806x/Kconfig | 22 ++++++++++++++++++++++ src/soc/qualcomm/ipq806x/Makefile.inc | 8 ++++++++ src/soc/qualcomm/ipq806x/cbfs.c | 26 ++++++++++++++++++++++++++ src/soc/qualcomm/ipq806x/timer.c | 28 ++++++++++++++++++++++++++++ 8 files changed, 89 insertions(+), 1 deletion(-)
diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 5903a57..53d7b90 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,3 +1,4 @@ source src/soc/intel/Kconfig source src/soc/nvidia/Kconfig -source src/soc/samsung/Kconfig \ No newline at end of file +source src/soc/qualcomm/Kconfig +source src/soc/samsung/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index b36d5be..6939346 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -3,4 +3,5 @@ ################################################################################ subdirs-y += intel subdirs-y += nvidia +subdirs-y += qualcomm subdirs-y += samsung diff --git a/src/soc/qualcomm/Kconfig b/src/soc/qualcomm/Kconfig new file mode 100644 index 0000000..b7a12d4 --- /dev/null +++ b/src/soc/qualcomm/Kconfig @@ -0,0 +1 @@ +source src/soc/qualcomm/ipq806x/Kconfig diff --git a/src/soc/qualcomm/Makefile.inc b/src/soc/qualcomm/Makefile.inc new file mode 100644 index 0000000..06b2f2f --- /dev/null +++ b/src/soc/qualcomm/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOC_QC_IPQ806X) += ipq806x diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig new file mode 100644 index 0000000..fcf8ccd --- /dev/null +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -0,0 +1,22 @@ +config SOC_QC_IPQ806X + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + bool + default n + +if SOC_QC_IPQ806X + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc new file mode 100644 index 0000000..be37581 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -0,0 +1,8 @@ +bootblock-y += cbfs.c +bootblock-y += timer.c + +romstage-y += cbfs.c +romstage-y += timer.c + +ramstage-y += cbfs.c +ramstage-y += timer.c diff --git a/src/soc/qualcomm/ipq806x/cbfs.c b/src/soc/qualcomm/ipq806x/cbfs.c new file mode 100644 index 0000000..97ae548 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbfs.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbfs.h> /* This driver serves as a CBFS media source. */ + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c new file mode 100644 index 0000000..c4e250e --- /dev/null +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void init_timer(void) +{ +} +
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Isaac Christensen