[XL] Change in coreboot[main]: soc/intel/ptl: Add GPIOs for Panther Lake SOC

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Elyes Haouas, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Paul Menzel, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim.

Hello Anil Kumar K, Bora Guvendik, Jamie Ryu, Jérémy Compostella, Kapil Porwal, Pranava Y N, Ravishankar Sarawadi, Saurabh Mishra, Subrata Banik, Wonkyu Kim, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/83789?usp=email

to look at the new patch set (#69).

Change subject: soc/intel/ptl: Add GPIOs for Panther Lake SOC
......................................................................

soc/intel/ptl: Add GPIOs for Panther Lake SOC

Add definitions for the GPIO pins on Panther Lake SoC,
as well as GPIO IRQ routing information and defines for ACPI ASL.

For now, add the following GPIO communities and GPIO groups:

Comm. 0: GPP_V, GPP_C
Comm. 1: GPP_F, GPP_E
Comm. 3: CPUJTAG, GPP_H, GPP_A, VGPIO3
Comm. 4: GPP_S
Comm. 5: GPP_B, GPP_D, VGPIO

BUG=b:348678529
TEST=Verify on Intel Silicon platform for PTL using google/fatcat
mainboard. Note that these GPIO changes cannot be verified along as
they are merely data structure and defines for the SOC. With the
GPIO ASL, we should see the following GPIO instances under
/sys/bus/acpi/devices when booting to OS:
INTC10BC:00/ INTC10BC:01/ INTC10BC:02/ INTC10BC:03/ INTC10BC:04/

Signed-off-by: Cliff Huang 
Change-Id: Iae1bc072841214efaec7a10719dbc742f2da795b
---
M src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/gpio.c
A src/soc/intel/pantherlake/include/soc/gpio.h
A src/soc/intel/pantherlake/include/soc/gpio_defs.h
A src/soc/intel/pantherlake/include/soc/gpio_soc_defs.h
5 files changed, 1,057 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83789/69