Change in coreboot[master]: soc/intel/baytrail: Drop runtime ACPI mode change via SMI

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Lance Zhao, Martin Roth, Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/49492 )

Change subject: soc/intel/baytrail: Drop runtime ACPI mode change via SMI
......................................................................

soc/intel/baytrail: Drop runtime ACPI mode change via SMI

This reverts commit 9afc5c05f

Change-Id: I76736fa72af30003d86dfc2551b673037c1dd522
Signed-off-by: Kyösti Mälkki 
---
M src/acpi/Makefile.inc
M src/soc/intel/baytrail/smihandler.c
2 files changed, 0 insertions(+), 63 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/49492/1

diff --git a/src/acpi/Makefile.inc b/src/acpi/Makefile.inc
index b91f7a4..1cd837d 100644
--- a/src/acpi/Makefile.inc
+++ b/src/acpi/Makefile.inc
@@ -19,9 +19,6 @@

postcar-y += acpi_pm.c

-/* TODO: Device runtime mode changes via SMI. */
-smm-$(CONFIG_SOC_INTEL_BAYTRAIL) += gnvs.c
-
 ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/acpi_tables.c),)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/acpi_tables.c
 endif
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index c2c6c91..037d5f1 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <stdint.h>
-#include <acpi/acpi_gnvs.h>
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
@@ -18,7 +17,6 @@
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/nvs.h>
-#include <soc/device_nvs.h>

int southbridge_io_trap_handler(int smif)
 {
@@ -206,61 +204,6 @@
    *ret = gsmi_exec(sub_command, param);
 }

-/*
- * soc_legacy: A payload (Depthcharge) has indicated that the
- *   legacy payload (SeaBIOS) is being loaded. Switch devices that are
- *   in ACPI mode to PCI mode so that non-ACPI drivers may work.
- *
- */
-static void soc_legacy(void)
-{
-	struct device_nvs *dev_nvs = acpi_get_device_nvs();
-	u32 reg32;
-
-	/* LPE Device */
-	if (dev_nvs->lpe_en) {
-		reg32 = iosf_port58_read(LPE_PCICFGCTR1);
-		reg32 &=
-		~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN);
-		iosf_port58_write(LPE_PCICFGCTR1, reg32);
-	}
-
-	/* SCC Devices */
-#define SCC_ACPI_MODE_DISABLE(name_) \
-	do { if (dev_nvs->scc_en[SCC_NVS_ ## name_]) { \
-		reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \
-		reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \
-		iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \
-	} } while (0)
-
-	SCC_ACPI_MODE_DISABLE(MMC);
-	SCC_ACPI_MODE_DISABLE(SD);
-	SCC_ACPI_MODE_DISABLE(SDIO);
-
-	 /* LPSS Devices */
-#define LPSS_ACPI_MODE_DISABLE(name_) \
-	do { if (dev_nvs->lpss_en[LPSS_NVS_ ## name_]) { \
-		reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \
-		reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \
-		iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \
-	} } while (0)
-
-	LPSS_ACPI_MODE_DISABLE(SIO_DMA1);
-	LPSS_ACPI_MODE_DISABLE(I2C1);
-	LPSS_ACPI_MODE_DISABLE(I2C2);
-	LPSS_ACPI_MODE_DISABLE(I2C3);
-	LPSS_ACPI_MODE_DISABLE(I2C4);
-	LPSS_ACPI_MODE_DISABLE(I2C5);
-	LPSS_ACPI_MODE_DISABLE(I2C6);
-	LPSS_ACPI_MODE_DISABLE(I2C7);
-	LPSS_ACPI_MODE_DISABLE(SIO_DMA2);
-	LPSS_ACPI_MODE_DISABLE(PWM1);
-	LPSS_ACPI_MODE_DISABLE(PWM2);
-	LPSS_ACPI_MODE_DISABLE(HSUART1);
-	LPSS_ACPI_MODE_DISABLE(HSUART2);
-	LPSS_ACPI_MODE_DISABLE(SPI);
-}
-
 static void southbridge_smi_store(void)
 {
    u8 sub_command, ret;
@@ -316,9 +259,6 @@
    	if (CONFIG(ELOG_GSMI))
    		southbridge_smi_gsmi();
    	break;
-	case APM_CNT_LEGACY:
-		soc_legacy();
-		break;
    case APM_CNT_SMMSTORE:
    	if (CONFIG(SMMSTORE))
    		southbridge_smi_store();