Change in coreboot[master]: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution

[Michał Żygowski (Code Review)]

Attention is currently required from: Michał Żygowski, Michał Kopeć.
Hello build bot (Jenkins), Michał Kopeć, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52781

to look at the new patch set (#8).

Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
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cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution

Create the correct MTRR solution based on the physical address space
provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not
account for lost C6 DRAM storage MTRR during postcar frame creation.
The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and
overlapping with usable DRAM WB MTRR. However this UC MTRR remained on
APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR
function to create correct MTRR solution that propagates to APs. This
also fixes the inconsistent MTRRs warning.

TEST=boot Debian with Linux 4.14 on apu1 2GB

Signed-off-by: Michał Żygowski 
Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be
Signed-off-by: Michał Kopeć 
---
M src/cpu/amd/agesa/family14/model_14_init.c
1 file changed, 33 insertions(+), 40 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/8