[S] Change in coreboot[main]: soc/intel/xeon_sp: Report PCIe integrated end points under DRHD

[Shuo Liu (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Hello Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84315?usp=email

to look at the new patch set (#2).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/xeon_sp: Report PCIe integrated end points under DRHD
......................................................................

soc/intel/xeon_sp: Report PCIe integrated end points under DRHD

In case of a PCH-less platform, no DRHD_INCLUDE_PCI_ALL flags are
used, all PCIe integrated end points should be explicitly listed
under its specific DRHD.

Change-Id: Ib015b002f2c077f50d48c046513504bdbd5b35aa
Signed-off-by: Jincheng Li 
---
M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 16 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84315/2