Attention is currently required from: Tim Wawrzynczak, Ravindra, Sridhar Siricilla, Mark Hsieh, Patrick Rudolph.
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61586 )
Change subject: soc/intel/alderlake, mb/google/brya: Update Type-C USB2 port config
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/include/soc/usb.h:
https://review.coreboot.org/c/coreboot/+/61586/comment/681a6fd7_96e6c26b
PS7, Line 97: /* Type-C Port, Max TX and Pre-emp settings */
Can we move all macro related changes in single patch here: https://review.coreboot.org/c/coreboot/+/61623/2?
It'll be easy to differentiate between soc and mainboard changes.
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