Change in coreboot[master]: soc/amd/cezanne: Preload FSP-S

[Paul Fagerburg (Code Review)]

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59025 )

Change subject: soc/amd/cezanne: Preload FSP-S
......................................................................

soc/amd/cezanne: Preload FSP-S

FSP-S is normally memmapped and then decompressed. There are about 7 ms
between starting ramstage, and loading FSP-S. By preloading we can
ensure the fsps.bin is already in RAM by the time we need it. This
reduces boot time by about 7 ms.

BUG=b:
TEST=Boot nipperkin and see ~7ms reduction in boot time
| 10 - start of ramstage                              | 0.044     | 0.044     Δ(  0.00,    0.00%) |
| 30 - device enumeration                             | 1.899     | 2.073     Δ(  0.17,    0.01%) |
| 971 - loading FSP-S                                 | 6.645     | 6.628     Δ( -0.02,   -0.00%) |
| 15 - starting LZMA decompress (ignore for x86)      | 0.016     | 0.01      Δ( -0.01,   -0.00%) |
| 16 - finished LZMA decompress (ignore for x86)      | 15.266    | 8.316     Δ( -6.95,   -0.47%) |
| 954 - calling FspSiliconInit                        | 0.08      | 0.09      Δ(  0.01,    0.00%) |

CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1)
CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208
waiting for thread
took 1 us <-- fsps.bin was preloaded
CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful

Signed-off-by: Raul E Rangel 
Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025
Tested-by: build bot (Jenkins) 
Reviewed-by: Karthik Ramasubramanian 
Reviewed-by: Rob Barnes 
---
M src/soc/amd/cezanne/Makefile.inc
A src/soc/amd/cezanne/preload.c
2 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Karthik Ramasubramanian: Looks good to me, approved
  Rob Barnes: Looks good to me, approved

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index 8db0f6c..58df740 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -39,6 +39,7 @@
 ramstage-y	+= graphics.c
 ramstage-y	+= i2c.c
 ramstage-y	+= mca.c
+ramstage-y	+= preload.c
 ramstage-y	+= reset.c
 ramstage-y	+= root_complex.c
 ramstage-y	+= uart.c
diff --git a/src/soc/amd/cezanne/preload.c b/src/soc/amd/cezanne/preload.c
new file mode 100644
index 0000000..d8b0891
--- /dev/null
+++ b/src/soc/amd/cezanne/preload.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootstate.h>
+#include <fsp/api.h>
+
+static void start_fsps_preload(void *unused)
+{
+	preload_fsps();
+}
+
+BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, start_fsps_preload, NULL);

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.