Attention is currently required from: Jérémy Compostella, Paul Menzel, Shuo Liu, yuchi.chen@intel.com.
Felix Singer has posted comments on this change by yuchi.chen@intel.com. ( https://review.coreboot.org/c/coreboot/+/83192?usp=email )
Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC ......................................................................
Patch Set 4:
(2 comments)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/824d4d3c_f3bd17fd?usp... : PS4, Line 29: This file is automatically generated. Please do NOT modify !!!
Please add to the commit message, how it was generated.
It's the same procedure for all FSP headers. Nothing new.
https://review.coreboot.org/c/coreboot/+/83192/comment/b9e46537_8b712d60?usp... : PS4, Line 100: This structure holds the DLL configuration : register values that will be programmed by RC. : Those policies should be used by platform if default values : provided by RC are not sufficient to provide stable operation : at all supported speed modes. RC will blindly set the DLL values : as provided in this structure.
The FSP headers are not own by my team, I'm asking my colleagues for help now, please wait for some […]
It's not a big issue. It can be updated with another update of the headers. I'm marking it as resolved.