Change in coreboot[master]: [Brya][Debug] src/mb/brya: Configure GPP_F17 as SCI

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63508 )

Change subject: [Brya][Debug] src/mb/brya: Configure GPP_F17 as SCI
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[Brya][Debug] src/mb/brya: Configure GPP_F17 as SCI

Change-Id: I4c2d5eee6a867104bc72f8f296fbaa5527aecf80
---
M src/mainboard/google/brya/variants/baseboard/brya/gpio.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/63508/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
index fb7bc21..9f63e73 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c
@@ -246,7 +246,8 @@
    /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
    PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
    /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
-	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
+	/*PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),*/
+	PAD_CFG_GPI_SCI_LOW(GPP_F17, NONE, PLTRST, EDGE_SINGLE),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
    PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
    /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */