Attention is currently required from: Jason Glenesk, EricKY Cheng, Matt DeVillier, Tim Van Patten, Fred Reitberger, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )
Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters ......................................................................
Patch Set 20:
(1 comment)
File src/soc/amd/mendocino/root_complex.c:
https://review.coreboot.org/c/coreboot/+/68649/comment/f3877970_91076827 PS20, Line 269: /* Normal mode DPTC values. */ : struct dptc_input default_input = DPTC_INPUTS( : config->thermctl_limit_degreeC, : config->sustained_power_limit_mW, : config->slow_ppt_time_constant_s, : config->fast_ppt_limit_mW, : config->slow_ppt_limit_mW, : config->vrm_current_limit_mA, : config->vrm_maximum_current_limit_mA, : config->vrm_soc_current_limit_mA, : config->stt_min_limit, : config->stt_m1, : config->stt_m2, : config->stt_c_apu, : config->stt_skin_temp_apu); : acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); : : /* Low/No Battery */ : struct dptc_input no_battery_input = DPTC_INPUTS( : config->thermctl_limit_degreeC, : config->sustained_power_limit_mW, : config->slow_ppt_time_constant_s, : config->fast_ppt_limit_mW, : config->slow_ppt_limit_mW, : config->vrm_current_limit_throttle_mA, : config->vrm_maximum_current_limit_throttle_mA, : config->vrm_soc_current_limit_throttle_mA, : config->stt_min_limit, : config->stt_m1, : config->stt_m2, : config->stt_c_apu, : config->stt_skin_temp_apu); : acpigen_write_alib_dptc_no_battery((uint8_t *)&no_battery_input, : sizeof(no_battery_input)); Delete these and use the ones defined below instead.