Change in coreboot[master]: sb/intel/i82801jx: set all* Chipset Initialization Registers (CIR) co...
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28053 )
Change subject: sb/intel/i82801jx: set all* Chipset Initialization Registers (CIR) correctly ......................................................................
Patch Set 3:
(1 comment)
I'll try to investigate on this. I suspect DMI is not properly set up.
https://review.coreboot.org/c/coreboot/+/28053/2/src/southbridge/intel/i8280... File src/southbridge/intel/i82801ix/i82801ix.c:
https://review.coreboot.org/c/coreboot/+/28053/2/src/southbridge/intel/i8280... PS2, Line 47: //(6 << 8) | (1 << 3) | (3 << 0);
Even exactly using the same code (regarding CIRs, BCR, FD, GCS) as i82801ix_dmi_setup() and i82801ix_early_settings() within i82801jx_early_settings() does produce the usb timeouts unless I don't touch CIR3. However, mind you, the vendor firmware does write 0x60b to it according to inteltool. Could it be some other bug, maybe even in seabios?
This also seems to happen with the ICH7 southbridge. Those bits in CIR3 are related to DMI private virtual channel routing (including EHCI, UHCI, AC '97 and azalia). So my guess would be that the DMI on the northbride and also possibly the southbridge side is not properly set up.
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Arthur Heymans (Code Review)