Attention is currently required from: Raul Rangel, Marshall Dawson, Paul Menzel, Matt Papageorge, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58198 )
Change subject: mb/google/guybrush: Add PCIe Reset GPIO69 to SD DXIO Descriptor
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/58198/comment/7052235a_684f97a0
PS1, Line 16: Cq-Depend: chrome-internal:4157948
Nit: Move this line right above Change-Id line.
File src/mainboard/google/guybrush/port_descriptors.c:
https://review.coreboot.org/c/coreboot/+/58198/comment/4530ca61_8a1c907e
PS1, Line 54: NVME
Do we need to specify the NVMe pin as well now?
SSD_AUX_RST_L/AGPIO40 is in S5 domain. So I dont think FSP passes that GPIO to SMU. It passes GPIOs in S0 domain only.
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