[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0

[Mario Scheithauer (Code Review)]

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh.

Hello Jan Samek, Paul Menzel, Werner Zeh, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/76175?usp=email

to look at the new patch set (#4).

The following approvals got outdated and were removed:
Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)

Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
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mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0

Because of an incorrect transmit voltage swing, the signal must be
adjusted. The factor of slices for full swing level can be corrected via
the High Speed I/O Transmit Control Register 3. The appropriate value of
0.7 V was determined by using an oscilloscope.

Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/76175/4