Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier.
Hello Fred Reitberger, Jason Glenesk, Matt DeVillier,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83446?usp=email
to look at the new patch set (#2).
Change subject: soc/amd/common/block/psp_gen2: add get_psp_mmio_base ......................................................................
soc/amd/common/block/psp_gen2: add get_psp_mmio_base
Add get_psp_mmio_base which reads the PSP MMIO base address from the hardware registers. Since this function will not only be called in ramstage, but also in SMM, we can't just look for the specific domain resource consumer like it is done for the IOAPICs in the northbridge, but have to get this base address from the registers. In order to limit the performance impact of this, the base address gets cached in a static variable if the hardware lock bit of the corresponding base address register is already set which means the base address can't change any more before the next reset.
This is a preparation to move back to using MMIO access to the PSP registers and will also enable cases that require the use of the MMIO mapping of the PSP registers.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I1d51e30f186508b0fe1ab5eb79c73e6d4b9d1a4a --- M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 66 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/83446/2