Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 16:
(7 comments)
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/ee65de6f_61b2fcf3?usp... :
PS16, Line 10: */
missing leading space.
Acknowledged
File src/soc/intel/pantherlake/include/soc/p2sb.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/f8cb0437_b0f4cb54?usp... :
PS16, Line 7: (1 << 7)
`BIT(7)` ?
Acknowledged
File src/soc/intel/pantherlake/include/soc/pci_devs.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/5a703496_021a7397?usp... :
PS16, Line 61: xb
0x0b
Acknowledged
https://review.coreboot.org/c/coreboot/+/83354/comment/0c7c32c1_c626d761?usp... :
PS16, Line 65: 0xc
0x0c
Acknowledged
https://review.coreboot.org/c/coreboot/+/83354/comment/811a66fb_fb8b28c3?usp... :
PS16, Line 219: #endif //_SOC_PANTHERLAKE_PCI_DEVS_H_
Shouldn't this be at the end of the file ?
Acknowledged
File src/soc/intel/pantherlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/84b7efeb_489a8165?usp... :
PS16, Line 8: #define PID_GPIOCOM0 0x59
Where do these PID values come from ?
These are referenced from HAS doc.
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/bcb449c8_923189c4?usp... :
PS16, Line 7: (1 << 15)
Could we use the `BIT` macro instead ?
Hi Jeremey, we can do it, i feel it can be done in the refactoring phase.
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