Change in coreboot[master]: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks

[Angel Pons (Code Review)]

Attention is currently required from: Michał Żygowski, Tim Wawrzynczak.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63457 )

Change subject: soc/intel/alderlake: Update maximum PCIe and TBT ports and clocks
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Patch Set 2: Code-Review+1