Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/25446 )
Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ......................................................................
soc/intel/denverton_ns: Generate ACPI DMAR Table
- Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings.
Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert jviarddegalbert@online.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/25446 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 78 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 944e8eb..e7d29ff 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -16,6 +16,7 @@ #include <soc/soc_util.h> #include <soc/pmc.h> #include <soc/systemagent.h> +#include <soc/pci_devs.h>
#define MWAIT_RES(state, sub_state) \ { \ @@ -268,3 +269,54 @@ }
__weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + uint64_t vtbar; + unsigned long tmp = current; + + vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; + printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar); + if (!vtbar) + return current; + + current += acpi_create_dmar_drhd(current, + DRHD_INCLUDE_PCI_ALL, 0, vtbar); + + current += acpi_create_dmar_ds_ioapic(current, + 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_msi_hpet(current, + 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, 0); + + acpi_dmar_drhd_fixup(tmp, current); + + /* Create RMRR; see "VTD PLATFORM CONFIGURATION" in FSP log */ + tmp = current; + current += acpi_create_dmar_rmrr(current, 0, + RMRR_USB_BASE_ADDRESS, + RMRR_USB_LIMIT_ADDRESS); + current += acpi_create_dmar_ds_pci(current, + 0, XHCI_DEV, XHCI_FUNC); + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +unsigned long systemagent_write_acpi_tables(const struct device *dev, + unsigned long current, + struct acpi_rsdp *const rsdp) +{ + /* Create DMAR table only if we have VT-d capability. */ + const u32 capid0_a = pci_read_config32(dev, CAPID0_A); + if (capid0_a & VTD_DISABLE) + return current; + + acpi_dmar_t *const dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + + return current; +} diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h index 9bc5ed0..86bed00 100644 --- a/src/soc/intel/denverton_ns/include/soc/acpi.h +++ b/src/soc/intel/denverton_ns/include/soc/acpi.h @@ -12,5 +12,8 @@ unsigned long current, struct acpi_rsdp *rsdp); void southcluster_inject_dsdt(const struct device *device); +unsigned long systemagent_write_acpi_tables(const struct device *dev, + unsigned long start, + struct acpi_rsdp *const rsdp);
#endif /* _DENVERTON_NS_ACPI_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/iomap.h b/src/soc/intel/denverton_ns/include/soc/iomap.h index 6e5f313..fb5aafd 100644 --- a/src/soc/intel/denverton_ns/include/soc/iomap.h +++ b/src/soc/intel/denverton_ns/include/soc/iomap.h @@ -24,4 +24,8 @@ #define DEFAULT_HPET_ADDR CONFIG_HPET_ADDRESS #define DEFAULT_SPI_BASE 0xfed01000
+/* "VTD PLATFORM CONFIGURATION" (Set to match FSP settings) */ +#define RMRR_USB_BASE_ADDRESS 0x3e2e0000 +#define RMRR_USB_LIMIT_ADDRESS 0x3e2fffff + #endif /* _DENVERTON_NS_IOMAP_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h index b6bac0b..5eac5bd 100644 --- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h +++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h @@ -143,4 +143,12 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_SPI _PCH_DEV(LPC, 5)
+/* VT-d support value to match FSP settings */ +/* "PCH IOAPIC Config" */ +#define PCH_IOAPIC_PCI_BUS 0xf0 +#define PCH_IOAPIC_PCI_SLOT 0x1f +/* "PCH HPET Config" */ +#define PCH_HPET_PCI_BUS 0 +#define PCH_HPET_PCI_SLOT 0 + #endif /* _DENVERTON_NS_PCI_DEVS_H_ */ diff --git a/src/soc/intel/denverton_ns/include/soc/systemagent.h b/src/soc/intel/denverton_ns/include/soc/systemagent.h index 561f482..0606a3e 100644 --- a/src/soc/intel/denverton_ns/include/soc/systemagent.h +++ b/src/soc/intel/denverton_ns/include/soc/systemagent.h @@ -31,6 +31,9 @@ #define TOLUD 0xbc /* Top of Low Used Memory */ #define MASK_TOLUD 0xFFF00000
+#define CAPID0_A 0xe4 +#define VTD_DISABLE (1 << 23) + /* SideBand B-UNIT */ #define B_UNIT 3
@@ -57,6 +60,10 @@ #define MCH_BMISC_RESDRAM \ 0x01 /* Bit 0: 1 - reads targeting E-segment are routed to DRAM. */
+#define MCH_VTBAR_OFFSET 0x6c80 +#define MCH_VTBAR_ENABLE_MASK 0x1 +#define MCH_VTBAR_MASK 0x7ffffff000 + #define MCH_BAR_BIOS_RESET_CPL 0x7078 #define RST_CPL_BIT (1 << 0) #define PCODE_INIT_DONE (1 << 8) diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index daac3eb..114ee48 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -15,6 +15,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> +#include <soc/acpi.h>
#define _1ms 1 #define WAITING_STEP 100 @@ -325,6 +326,9 @@ .enable_resources = pci_dev_enable_resources, .init = systemagent_init, .ops_pci = &soc_pci_ops, +#if CONFIG(HAVE_ACPI_TABLES) + .write_acpi_tables = systemagent_write_acpi_tables, +#endif };
/* IDs for System Agent device of Intel Denverton SoC */
-
Patrick Georgi (Code Review)