[XS] Change in coreboot[main]: mb/google/brya/var/nova: Configure scaler I2C GPIOs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84091?usp=email )

Change subject: mb/google/brya/var/nova: Configure scaler I2C GPIOs
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mb/google/brya/var/nova: Configure scaler I2C GPIOs

According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL).

BUG=b:358439747
TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C.

Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b
Signed-off-by: Kenneth Chan 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091
Reviewed-by: David Wu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Eric Lai 
Reviewed-by: Dinesh Gehlot 
---
M src/mainboard/google/brya/variants/nova/gpio.c
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  Dinesh Gehlot: Looks good to me, approved
  build bot (Jenkins): Verified
  David Wu: Looks good to me, approved
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brya/variants/nova/gpio.c b/src/mainboard/google/brya/variants/nova/gpio.c
index e895244..ce4d11d 100644
--- a/src/mainboard/google/brya/variants/nova/gpio.c
+++ b/src/mainboard/google/brya/variants/nova/gpio.c
@@ -91,6 +91,10 @@
    /* F16 : GSXCLK ==> MEM_STRAP_0 */
    PAD_CFG_GPI_LOCK(GPP_F16, NONE, LOCK_CONFIG),

+	/* H4  : I2C0_SDA ==> PCH_I2C_SCALER_SDA */
+	PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
+	/* H5  : I2C0_SCL ==> PCH_I2C_SCALER_SCL */
+	PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
    /* H12 : I2C7_SDA ==> NC */
    PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
    /* H13 : I2C7_SCL ==> NC */