[XS] Change in coreboot[main]: mb/google/brox/variants/brox: Update PL1 Min

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83661?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: mb/google/brox/variants/brox: Update PL1 Min
......................................................................

mb/google/brox/variants/brox: Update PL1 Min

Update PL1 Min value from 6W to 15W based on the brox thermal cooling
capacity and hardware design.

BUG=None
BRANCH=None
TEST=Build and boot on brox board

Signed-off-by: Sumeet Pawnikar 
Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/brox/variants/brox/ramstage.c
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved

diff --git a/src/mainboard/google/brox/variants/brox/ramstage.c b/src/mainboard/google/brox/variants/brox/ramstage.c
index c81dd7e..78e03ca 100644
--- a/src/mainboard/google/brox/variants/brox/ramstage.c
+++ b/src/mainboard/google/brox/variants/brox/ramstage.c
@@ -16,7 +16,7 @@
    {
    	.mchid = PCI_DID_INTEL_RPL_P_ID_3,
    	.cpu_tdp = 15,
-		.pl1_min_power = 6000,
+		.pl1_min_power = 15000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 55000,
    	.pl2_max_power = 55000,
@@ -25,7 +25,7 @@
    {
    	.mchid = PCI_DID_INTEL_RPL_P_ID_4,
    	.cpu_tdp = 15,
-		.pl1_min_power = 6000,
+		.pl1_min_power = 15000,
    	.pl1_max_power = 15000,
    	.pl2_min_power = 55000,
    	.pl2_max_power = 55000,