[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Adjust WWAN GPIO enable sequence for DV...

[Roger Wang (Code Review)]

Roger Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83792?usp=email )

Change subject: mb/google/nissa/var/sundance: Adjust WWAN GPIO enable sequence for DVT build
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mb/google/nissa/var/sundance: Adjust WWAN GPIO enable sequence for DVT build

Remove the WWAN_RST_L (GPP_F12) in bootblock phase

BUG=b:357764679
TEST=Build and verified test result by EE team

Change-Id: I2c0e789c0bec293f4bca711e53644d62f4f83551
Signed-off-by: Roger Wang 
---
M src/mainboard/google/brya/variants/sundance/gpio.c
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83792/1

diff --git a/src/mainboard/google/brya/variants/sundance/gpio.c b/src/mainboard/google/brya/variants/sundance/gpio.c
index bd36f05..107fa77 100644
--- a/src/mainboard/google/brya/variants/sundance/gpio.c
+++ b/src/mainboard/google/brya/variants/sundance/gpio.c
@@ -66,8 +66,6 @@
    PAD_CFG_GPO(GPP_D6, 0, DEEP),
    /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
    PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
-	/* F12 : WWAN_RST_L */
-	PAD_CFG_GPO(GPP_F12, 0, DEEP),
    /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
    PAD_CFG_GPI(GPP_F18, NONE, DEEP),
    /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */