[L] Change in coreboot[main]: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support

[Angel Pons (Code Review)]

Attention is currently required from: Alicja Michalska, David Milosevic, Felix Singer, Lean Sheng Tan.

Angel Pons has posted comments on this change by David Milosevic. ( https://review.coreboot.org/c/coreboot/+/83979?usp=email )

Change subject: [WIP] mb/hardkernel/odroid-h4: add initial odroid-h4 support
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Patch Set 4: Code-Review+1

(10 comments)

Patchset:

PS2:
> i think we also support odroid-h4 plus too, should you add this as another variant?

What are the differences? If possible I'd try to avoid creating variants (different firmware builds) and instead have the same coreboot target for H4, H4 plus and whatever

File src/mainboard/hardkernel/odroid-h4/Kconfig:

https://review.coreboot.org/c/coreboot/+/83979/comment/5d0806d3_081cff3b?usp... :
PS4, Line 37: config NO_POST
            : 	default y
            : 
There's a FFC (Flat Flexible Cable) connector on the bottom of the board named "ESPI_DEBUG1", so I would keep POST codes enabled in case someone needs them to debug.

File src/mainboard/hardkernel/odroid-h4/bootblock.c:

https://review.coreboot.org/c/coreboot/+/83979/comment/ecab88b1_2f372e70?usp... :
PS4, Line 13: 	ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10
What is GP10 used for? Seems unused on both schematics and in vendor firmware default settings (0x00, same as chip default). Please remove

https://review.coreboot.org/c/coreboot/+/83979/comment/9c91ab83_738f1d21?usp... :
PS4, Line 14: 	ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31
GP31 is used as CTS# so this should be removed too

https://review.coreboot.org/c/coreboot/+/83979/comment/84009726_e4393a4a?usp... :
PS4, Line 15: 	ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40
This seems to be used as PWRGD3, going to SYS_PWROK. I think this should be removed.

https://review.coreboot.org/c/coreboot/+/83979/comment/360e260e_38a15045?usp... :
PS4, Line 16: Enable Pin GP50
This is not GP50 (doesn't appear in the schematics), but the value matches vendor firmware.

File src/mainboard/hardkernel/odroid-h4/gpio.h:

https://review.coreboot.org/c/coreboot/+/83979/comment/96b25019_e42b3db7?usp... :
PS4, Line 96: 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),	/* UART0_TXD */
This is not used

File src/mainboard/hardkernel/odroid-h4/ramstage_fsp_params.c:

PS4: 
No license header

https://review.coreboot.org/c/coreboot/+/83979/comment/22b87964_407e1fa0?usp... :
PS4, Line 4: 
           : 	fsp_s_config->PchLegacyIoLowLatency = 1;
           : 	fsp_s_config->PchDmiAspmCtrl = 0;
Why?

File src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c:

https://review.coreboot.org/c/coreboot/+/83979/comment/8463c89f_78647279?usp... :
PS4, Line 29: TODO: Implement __weak variant_is_half_populated(void) function.
Copy-pasta? This board has no variants, so this doesn't make much sense