Change in coreboot[master]: mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58213 )

Change subject: mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B
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mb/google/brya: Set same size for CSE_RW, ME_RW_A and ME_RW_B

CSE RW firmware from ME_RW_A/ME_RW_B is copied over to CSE_RW region
in case of firmware update. Ensure that the size of the regions match
so that we do not have situations where ME_RW_A/B firmware grows
bigger than what CSE_RW can hold.

BUG=b:189177538

Change-Id: I374db5d490292eeb98f67dc684c2106d42779dac
Signed-off-by: Furquan Shaikh 
---
M src/mainboard/google/brya/chromeos.fmd
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/58213/1

diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd
index 656b65b..fee1a53 100644
--- a/src/mainboard/google/brya/chromeos.fmd
+++ b/src/mainboard/google/brya/chromeos.fmd
@@ -5,7 +5,7 @@
    		CSE_LAYOUT 8K
    		CSE_RO 1600K
    		CSE_DATA 512K
-			CSE_RW
+			CSE_RW 2996K
    	}
    }
    SI_BIOS 27M {
@@ -13,7 +13,7 @@
    		VBLOCK_A 64K
    		FW_MAIN_A(CBFS)
    		RW_FWID_A 64
-			ME_RW_A(CBFS) 3M
+			ME_RW_A(CBFS) 2996K
    	}
    	RW_LEGACY(CBFS) 2M
    	RW_MISC 1M {
@@ -42,7 +42,7 @@
    		VBLOCK_B 64K
    		FW_MAIN_B(CBFS)
    		RW_FWID_B 64
-			ME_RW_B(CBFS) 3M
+			ME_RW_B(CBFS) 2996K
    	}
    	# Make WP_RO region align with SPI vendor
    	# memory protected range specification.