[XS] Change in coreboot[main]: soc/intel/pantherlake: Rename GSPI2 to GSPI0A

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85685?usp=email )

Change subject: soc/intel/pantherlake: Rename GSPI2 to GSPI0A
......................................................................

soc/intel/pantherlake: Rename GSPI2 to GSPI0A

Rename GSPI2 to GSPI0A to align with the latest Intel documentation
and platform specifications (doc: 815002)

BUG=b:377595986
TEST=Able to see 0x12.6 device is visible using `lspci`.

Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685
Tested-by: build bot (Jenkins) 
Reviewed-by: Pranava Y N 
Reviewed-by: YH Lin 
---
M src/soc/intel/pantherlake/chipset.cb
M src/soc/intel/pantherlake/include/soc/serialio.h
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  Pranava Y N: Looks good to me, approved
  YH Lin: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb
index 67e0785..0f7967b 100644
--- a/src/soc/intel/pantherlake/chipset.cb
+++ b/src/soc/intel/pantherlake/chipset.cb
@@ -90,7 +90,7 @@
    	device pci 10.1 alias thc1 off end
    	device pci 12.0 alias ish off end
    	device pci 12.1 alias p2sb2 hidden end
-		device pci 12.6 alias gspi2 off end
+		device pci 12.6 alias gspi0a off end
    	device pci 13.0 alias heci_1 off end
    	device pci 13.1 alias heci_2 off end
    	device pci 13.2 alias heci_3 off end
diff --git a/src/soc/intel/pantherlake/include/soc/serialio.h b/src/soc/intel/pantherlake/include/soc/serialio.h
index def5565..1c15001 100644
--- a/src/soc/intel/pantherlake/include/soc/serialio.h
+++ b/src/soc/intel/pantherlake/include/soc/serialio.h
@@ -23,7 +23,7 @@
 enum {
    PchSerialIoIndexGSPI0,
    PchSerialIoIndexGSPI1,
-	PchSerialIoIndexGSPI2,
+	PchSerialIoIndexGSPI0A,
 };

enum {