Attention is currently required from: Angel Pons.
Anastasios Koutian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83298?usp=email )
Change subject: src/{cpu,northbridge}: apply clang-format to files ......................................................................
src/{cpu,northbridge}: apply clang-format to files
Apply changes suggested by checkpatch hook
Change-Id: I776fe392a7542ab239f6968c2417e30e7af0fdfd --- M src/cpu/intel/model_206ax/chip.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_206ax/model_206ax_init.c M src/northbridge/intel/sandybridge/northbridge.c 4 files changed, 163 insertions(+), 201 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/83298/1
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h index 78a351b..838d2a7 100644 --- a/src/cpu/intel/model_206ax/chip.h +++ b/src/cpu/intel/model_206ax/chip.h @@ -18,7 +18,7 @@
/* VR12 PSI codes */ enum vr12_phases { - VR12_KEEP_DEFAULT = 0, /* For device-trees missing the setting */ + VR12_KEEP_DEFAULT = 0, /* For device-trees missing the setting */ VR12_ALL_PHASES, VR12_2_PHASES, VR12_1_PHASE, @@ -35,7 +35,7 @@
struct psi_state { enum vr12_phases phases; - int current; /* In Amps */ + int current; /* In Amps */ };
struct cpu_intel_model_206ax_config { @@ -43,19 +43,19 @@ enum cpu_acpi_level acpi_c2; enum cpu_acpi_level acpi_c3;
- int tcc_offset; /* TCC Activation Offset */ + int tcc_offset; /* TCC Activation Offset */
unsigned int pl1_mw; /* Long-term power limit in milliwatts */ - bool pl1_clamp; /* Long-term power limit clamping limitation */ + bool pl1_clamp; /* Long-term power limit clamping limitation */ unsigned int pl2_mw; /* Short-term power limit in milliwatts */ - bool pl2_clamp; /* Short-term power limit clamping limitation */ + bool pl2_clamp; /* Short-term power limit clamping limitation */
- int pp0_current_limit; /* Primary Plane Current Limit (Icc) in Amps */ - int pp1_current_limit; /* Secondary Plane Current Limit (IAXG) in Amps */ + int pp0_current_limit; /* Primary Plane Current Limit (Icc) in Amps */ + int pp1_current_limit; /* Secondary Plane Current Limit (IAXG) in Amps */
/* PSI states only have an effect when in Package C3 or higher */ - struct psi_state pp0_psi[3]; /* Power states for Primary Plane (Icc) */ - struct psi_state pp1_psi[3]; /* Power states for Secondary Plane (IAXG) */ + struct psi_state pp0_psi[3]; /* Power states for Primary Plane (Icc) */ + struct psi_state pp1_psi[3]; /* Power states for Secondary Plane (IAXG) */
int turbo_ratio_limit_1c; /* Turbo Ratio Limit for 1 core active */ int turbo_ratio_limit_2c; /* Turbo Ratio Limit for 2 cores active */ diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index d9fdcc4..ea5cbae 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -7,20 +7,20 @@ #include <stdint.h>
/* SandyBridge CPU stepping */ -#define SNB_STEP_B2 2 -#define SNB_STEP_C0 3 -#define SNB_STEP_D0 5 /* Also J0 */ -#define SNB_STEP_D1 6 -#define SNB_STEP_D2 7 /* Also J1/Q0 */ +#define SNB_STEP_B2 2 +#define SNB_STEP_C0 3 +#define SNB_STEP_D0 5 /* Also J0 */ +#define SNB_STEP_D1 6 +#define SNB_STEP_D2 7 /* Also J1/Q0 */
/* IvyBridge CPU stepping */ -#define IVB_STEP_A0 0 -#define IVB_STEP_B0 2 -#define IVB_STEP_C0 4 -#define IVB_STEP_K0 5 -#define IVB_STEP_D0 6 -#define IVB_STEP_E0 8 -#define IVB_STEP_E1 9 +#define IVB_STEP_A0 0 +#define IVB_STEP_B0 2 +#define IVB_STEP_C0 4 +#define IVB_STEP_K0 5 +#define IVB_STEP_D0 6 +#define IVB_STEP_E0 8 +#define IVB_STEP_E1 9
#define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) #define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) @@ -35,94 +35,94 @@ #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ -#define SANDYBRIDGE_BCLK 100 +#define SANDYBRIDGE_BCLK 100
-#define MSR_CORE_THREAD_COUNT 0x35 -#define MSR_FEATURE_CONFIG 0x13c -#define MSR_FLEX_RATIO 0x194 -#define FLEX_RATIO_LOCK (1 << 20) -#define FLEX_RATIO_EN (1 << 16) -#define MSR_TEMPERATURE_TARGET 0x1a2 -#define MSR_LT_LOCK_MEMORY 0x2e7 -#define MSR_PLATFORM_INFO 0xce -#define PLATFORM_INFO_SET_TDP (1 << 29) -#define PLATFORM_INFO_SET_TURBO_RATIO_LIMIT (1 << 28) +#define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_FEATURE_CONFIG 0x13c +#define MSR_FLEX_RATIO 0x194 +#define FLEX_RATIO_LOCK (1 << 20) +#define FLEX_RATIO_EN (1 << 16) +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_LT_LOCK_MEMORY 0x2e7 +#define MSR_PLATFORM_INFO 0xce +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define PLATFORM_INFO_SET_TURBO_RATIO_LIMIT (1 << 28)
-#define MSR_MISC_PWR_MGMT 0x1aa -#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) -#define MSR_TURBO_RATIO_LIMIT 0x1ad -#define MSR_POWER_CTL 0x1fc +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc
-#define MSR_PKGC3_IRTL 0x60a -#define MSR_PKGC6_IRTL 0x60b -#define MSR_PKGC7_IRTL 0x60c -#define IRTL_VALID (1 << 15) -#define IRTL_1_NS (0 << 10) -#define IRTL_32_NS (1 << 10) -#define IRTL_1024_NS (2 << 10) -#define IRTL_32768_NS (3 << 10) -#define IRTL_1048576_NS (4 << 10) -#define IRTL_33554432_NS (5 << 10) -#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_PKGC3_IRTL 0x60a +#define MSR_PKGC6_IRTL 0x60b +#define MSR_PKGC7_IRTL 0x60c +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff)
/* long duration in low dword, short duration in high dword */ -#define MSR_PKG_POWER_LIMIT 0x610 -#define PKG_POWER_LIMIT_MASK 0x7fff -#define PKG_POWER_LIMIT_EN (1 << 15) -#define PKG_POWER_LIMIT_CLAMP (1 << 16) -#define PKG_POWER_LIMIT_TIME_SHIFT 17 -#define PKG_POWER_LIMIT_TIME_MASK 0x7f +#define MSR_PKG_POWER_LIMIT 0x610 +#define PKG_POWER_LIMIT_MASK 0x7fff +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK 0x7f
-#define MSR_PP0_CURRENT_CONFIG 0x601 -#define PP0_CURRENT_LIMIT_LOCK (1U << 31) -#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ -#define MSR_PP1_CURRENT_CONFIG 0x602 -#define PP1_CURRENT_LIMIT_LOCK (1U << 31) -#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ -#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ -#define MSR_PKG_POWER_SKU_UNIT 0x606 -#define MSR_PKG_POWER_SKU 0x614 -#define MSR_PP0_POWER_LIMIT 0x638 -#define MSR_PP1_POWER_LIMIT 0x640 +#define MSR_PP0_CURRENT_CONFIG 0x601 +#define PP0_CURRENT_LIMIT_LOCK (1U << 31) +#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */ +#define MSR_PP1_CURRENT_CONFIG 0x602 +#define PP1_CURRENT_LIMIT_LOCK (1U << 31) +#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */ +#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */ +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_PP0_POWER_LIMIT 0x638 +#define MSR_PP1_POWER_LIMIT 0x640
-#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 -#define MSR_CONFIG_TDP_NOMINAL 0x648 -#define MSR_CONFIG_TDP_LEVEL1 0x649 -#define MSR_CONFIG_TDP_LEVEL2 0x64a -#define MSR_CONFIG_TDP_CONTROL 0x64b -#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c
/* P-state configuration */ -#define PSS_MAX_ENTRIES 8 -#define PSS_RATIO_STEP 2 -#define PSS_LATENCY_TRANSITION 10 -#define PSS_LATENCY_BUSMASTER 10 +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10
/* Sanity check config options. */ #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)) -# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" +#error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)" #endif #if (CONFIG_SMM_TSEG_SIZE < 0x800000) -# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" +#error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" #endif #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) -# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#error "CONFIG_SMM_TSEG_SIZE is not a power of 2" #endif #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) -# error "CONFIG_IED_REGION_SIZE is not a power of 2" +#error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif
/* * List of supported C-states for Sandy Bridge/Ivy Bridge. */ enum { - C_STATE_C0 = 0, - C_STATE_C1 = 1, - C_STATE_C1E = 2, - C_STATE_C3 = 3, - C_STATE_C6 = 4, - C_STATE_C7 = 5, - C_STATE_C7S = 6, + C_STATE_C0 = 0, + C_STATE_C1 = 1, + C_STATE_C1E = 2, + C_STATE_C3 = 3, + C_STATE_C6 = 4, + C_STATE_C7 = 5, + C_STATE_C7S = 6, NUM_C_STATES, };
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index c5b5d8e..a2a2cdb 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -21,60 +21,20 @@
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { - [0] = 0x00, - [1] = 0x0a, - [2] = 0x0b, - [3] = 0x4b, - [4] = 0x0c, - [5] = 0x2c, - [6] = 0x4c, - [7] = 0x6c, - [8] = 0x0d, - [10] = 0x2d, - [12] = 0x4d, - [14] = 0x6d, - [16] = 0x0e, - [20] = 0x2e, - [24] = 0x4e, - [28] = 0x6e, - [32] = 0x0f, - [40] = 0x2f, - [48] = 0x4f, - [56] = 0x6f, - [64] = 0x10, - [80] = 0x30, - [96] = 0x50, - [112] = 0x70, - [128] = 0x11, + [0] = 0x00, [1] = 0x0a, [2] = 0x0b, [3] = 0x4b, [4] = 0x0c, + [5] = 0x2c, [6] = 0x4c, [7] = 0x6c, [8] = 0x0d, [10] = 0x2d, + [12] = 0x4d, [14] = 0x6d, [16] = 0x0e, [20] = 0x2e, [24] = 0x4e, + [28] = 0x6e, [32] = 0x0f, [40] = 0x2f, [48] = 0x4f, [56] = 0x6f, + [64] = 0x10, [80] = 0x30, [96] = 0x50, [112] = 0x70, [128] = 0x11, };
/* Convert POWER_LIMIT_1_TIME MSR value to seconds */ static const u8 power_limit_time_msr_to_sec[] = { - [0x00] = 0, - [0x0a] = 1, - [0x0b] = 2, - [0x4b] = 3, - [0x0c] = 4, - [0x2c] = 5, - [0x4c] = 6, - [0x6c] = 7, - [0x0d] = 8, - [0x2d] = 10, - [0x4d] = 12, - [0x6d] = 14, - [0x0e] = 16, - [0x2e] = 20, - [0x4e] = 24, - [0x6e] = 28, - [0x0f] = 32, - [0x2f] = 40, - [0x4f] = 48, - [0x6f] = 56, - [0x10] = 64, - [0x30] = 80, - [0x50] = 96, - [0x70] = 112, - [0x11] = 128, + [0x00] = 0, [0x0a] = 1, [0x0b] = 2, [0x4b] = 3, [0x0c] = 4, + [0x2c] = 5, [0x4c] = 6, [0x6c] = 7, [0x0d] = 8, [0x2d] = 10, + [0x4d] = 12, [0x6d] = 14, [0x0e] = 16, [0x2e] = 20, [0x4e] = 24, + [0x6e] = 28, [0x0f] = 32, [0x2f] = 40, [0x4f] = 48, [0x6f] = 56, + [0x10] = 64, [0x30] = 80, [0x50] = 96, [0x70] = 112, [0x11] = 128, };
int cpu_config_tdp_levels(void) @@ -146,8 +106,8 @@ limit.lo |= PKG_POWER_LIMIT_CLAMP; } limit.lo |= PKG_POWER_LIMIT_EN; - limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) << - PKG_POWER_LIMIT_TIME_SHIFT; + limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) + << PKG_POWER_LIMIT_TIME_SHIFT;
limit.hi = 0; if (conf->pl2_mw) { @@ -177,29 +137,29 @@
static void configure_turbo_ratio_limits(struct cpu_intel_model_206ax_config *conf) { - msr_t msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + msr_t msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
- if (conf->turbo_ratio_limit_1c) { - msr.lo &= ~0xff; - msr.lo |= (conf->turbo_ratio_limit_1c); - } + if (conf->turbo_ratio_limit_1c) { + msr.lo &= ~0xff; + msr.lo |= (conf->turbo_ratio_limit_1c); + }
- if (conf->turbo_ratio_limit_2c) { - msr.lo &= ~(0xff << 8); - msr.lo |= (conf->turbo_ratio_limit_2c << 8); - } + if (conf->turbo_ratio_limit_2c) { + msr.lo &= ~(0xff << 8); + msr.lo |= (conf->turbo_ratio_limit_2c << 8); + }
- if (conf->turbo_ratio_limit_3c) { - msr.lo &= ~(0xff << 16); - msr.lo |= (conf->turbo_ratio_limit_3c << 16); - } + if (conf->turbo_ratio_limit_3c) { + msr.lo &= ~(0xff << 16); + msr.lo |= (conf->turbo_ratio_limit_3c << 16); + }
- if (conf->turbo_ratio_limit_4c) { - msr.lo &= ~(0xff << 24); - msr.lo |= (conf->turbo_ratio_limit_4c << 24); - } + if (conf->turbo_ratio_limit_4c) { + msr.lo &= ~(0xff << 24); + msr.lo |= (conf->turbo_ratio_limit_4c << 24); + }
- wrmsr(MSR_TURBO_RATIO_LIMIT, msr); + wrmsr(MSR_TURBO_RATIO_LIMIT, msr); }
static void configure_c_states(struct device *dev) @@ -208,14 +168,14 @@ msr_t msr;
msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 28); // C1 Auto Undemotion Enable - msr.lo |= (1 << 27); // C3 Auto Undemotion Enable - msr.lo |= (1 << 26); // C1 Auto Demotion Enable - msr.lo |= (1 << 25); // C3 Auto Demotion Enable - msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection - msr.lo |= 7; // No package C-state limit + msr.lo |= (1 << 28); // C1 Auto Undemotion Enable + msr.lo |= (1 << 27); // C3 Auto Undemotion Enable + msr.lo |= (1 << 26); // C1 Auto Demotion Enable + msr.lo |= (1 << 25); // C3 Auto Demotion Enable + msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection + msr.lo |= 7; // No package C-state limit
- msr.lo |= (1 << 15); // Lock C-State MSR + msr.lo |= (1 << 15); // Lock C-State MSR wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
if (boot_cpu()) { @@ -225,13 +185,13 @@ */
msr = rdmsr(MSR_MISC_PWR_MGMT); - msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination + msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination wrmsr(MSR_MISC_PWR_MGMT, msr);
msr = rdmsr(MSR_POWER_CTL); - msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 - msr.lo |= (1 << 1); // C1E Enable - msr.lo |= (1 << 0); // Bi-directional PROCHOT# + msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0 + msr.lo |= (1 << 1); // C1E Enable + msr.lo |= (1 << 0); // Bi-directional PROCHOT# wrmsr(MSR_POWER_CTL, msr);
/* C3 Interrupt Response Time Limit */ @@ -265,7 +225,8 @@ /* Fill in board specific maximum current supported by VR */ msr.lo |= conf->pp0_current_limit * 8; } else { - printk(BIOS_INFO, "%s: PP0 current limit not set in devicetree\n", dev_path(dev)); + printk(BIOS_INFO, "%s: PP0 current limit not set in devicetree\n", + dev_path(dev)); /* * The default value might over-stress the voltage regulator or * prevent OC on boards with regulators that can handle currents @@ -284,7 +245,8 @@ msr.hi |= (conf->pp0_psi[i].phases - 1) << (i * 10 + 7); msr.hi |= conf->pp0_psi[i].current << (i * 10); } else { - printk(BIOS_INFO, "%s: PP0 PSI%d not set in devicetree\n", dev_path(dev), i); + printk(BIOS_INFO, "%s: PP0 PSI%d not set in devicetree\n", + dev_path(dev), i); } } msr.lo |= PP0_CURRENT_LIMIT_LOCK; @@ -297,7 +259,8 @@ /* Fill in board specific maximum current supported by VR */ msr.lo |= conf->pp1_current_limit * 8; } else { - printk(BIOS_INFO, "%s: PP1 current limit not set in devicetree\n", dev_path(dev)); + printk(BIOS_INFO, "%s: PP1 current limit not set in devicetree\n", + dev_path(dev)); /* * The default value might over-stress the voltage regulator or * prevent OC on boards with regulators that can handle currents @@ -319,7 +282,8 @@ msr.hi |= (conf->pp1_psi[i].phases - 1) << (i * 10 + 7); msr.hi |= conf->pp1_psi[i].current << (i * 10); } else { - printk(BIOS_INFO, "%s: PP1 PSI%d not set in devicetree\n", dev_path(dev), i); + printk(BIOS_INFO, "%s: PP1 PSI%d not set in devicetree\n", + dev_path(dev), i); } } msr.lo |= PP1_CURRENT_LIMIT_LOCK; @@ -330,7 +294,8 @@ if (msr.lo & PLATFORM_INFO_SET_TURBO_RATIO_LIMIT) { configure_turbo_ratio_limits(conf); } else { - printk(BIOS_NOTICE, "%s: Programmable ratio limit for turbo mode is disabled\n", dev_path(dev)); + printk(BIOS_NOTICE, "%s: Programmable ratio limit for turbo mode is disabled\n", + dev_path(dev)); } }
@@ -361,9 +326,9 @@ msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 0); /* Fast String enable */ - msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + msr.lo |= (1 << 0); /* Fast String enable */ + msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ @@ -507,8 +472,7 @@ msr = rdmsr(MSR_CORE_THREAD_COUNT); num_threads = (msr.lo >> 0) & 0xffff; num_cores = (msr.lo >> 16) & 0xffff; - printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", - num_cores, num_threads); + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", num_cores, num_threads);
return num_threads; } @@ -557,16 +521,16 @@ }
static struct device_operations cpu_dev_ops = { - .init = model_206ax_init, + .init = model_206ax_init, };
static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x206a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel Sandybridge */ - { X86_VENDOR_INTEL, 0x306a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel IvyBridge */ + {X86_VENDOR_INTEL, 0x206a0, CPUID_ALL_STEPPINGS_MASK}, /* Intel Sandybridge */ + {X86_VENDOR_INTEL, 0x306a0, CPUID_ALL_STEPPINGS_MASK}, /* Intel IvyBridge */ CPU_TABLE_END };
static const struct cpu_driver driver __cpu_driver = { - .ops = &cpu_dev_ops, + .ops = &cpu_dev_ops, .id_table = cpu_table, }; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 3db9086..4041bb9 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -53,11 +53,11 @@ }
struct device_operations sandybridge_pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .scan_bus = pci_host_bridge_scan_bus, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .scan_bus = pci_host_bridge_scan_bus, .write_acpi_tables = northbridge_write_acpi_tables, - .acpi_name = northbridge_acpi_name, + .acpi_name = northbridge_acpi_name, };
static void add_fixed_resources(struct device *dev, int index) @@ -130,21 +130,20 @@ */
/* Top of Upper Usable DRAM, including remap */ - touud = get_touud(dev); + touud = get_touud(dev);
/* Top of Lower Usable DRAM */ tolud = pci_read_config32(dev, TOLUD);
/* Top of Memory - does not account for any UMA */ - tom = pci_read_config32(dev, TOM + 4); + tom = pci_read_config32(dev, TOM + 4); tom <<= 32; tom |= pci_read_config32(dev, TOM);
- printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", - touud, tolud, tom); + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", touud, tolud, tom);
/* ME UMA needs excluding if total memory < 4GB */ - me_base = pci_read_config32(dev, MESEG_BASE + 4); + me_base = pci_read_config32(dev, MESEG_BASE + 4); me_base <<= 32; me_base |= pci_read_config32(dev, MESEG_BASE);
@@ -160,8 +159,7 @@ /* UMA starts at old TOLUD */ uma_memory_base = tomk * 1024ULL; uma_memory_size = uma_size * 1024ULL; - printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", - me_base, uma_size >> 10); + printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n", me_base, uma_size >> 10); }
/* Graphics memory comes next */ @@ -391,19 +389,19 @@ }
struct device_operations sandybridge_host_bridge_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .ops_pci = &pci_dev_ops_pci, - .acpi_fill_ssdt = mc_gen_ssdt, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .ops_pci = &pci_dev_ops_pci, + .acpi_fill_ssdt = mc_gen_ssdt, };
struct device_operations sandybridge_cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = mp_cpu_bus_init, - .acpi_fill_ssdt = generate_cpu_entries, + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .init = mp_cpu_bus_init, + .acpi_fill_ssdt = generate_cpu_entries, };
struct chip_operations northbridge_intel_sandybridge_ops = {
-
Anastasios Koutian (Code Review)