Change in coreboot[master]: soc/intel/skylake: Set xtal bypass on low power idle

[Naresh Solanki (Code Review)]

Hello Aaron Durbin, Subrata Banik, Paul Menzel, build bot (Jenkins),

I'd like you to reexamine a change.  Please visit

https://review.coreboot.org/19442

to look at the new patch set (#7).

Change subject: soc/intel/skylake: Set xtal bypass on low power idle
......................................................................

soc/intel/skylake: Set xtal bypass on low power idle

When using Wake On Voice &/or DCI, it requires xtal to be active during
low power idle.

With xtal being active  in S0ix state power impact is 1-2 mW.

Hence set xtal bypass bit in CIR31C for low power idle entry.

TEST= Build with s0ix enable for Poppy. Boot to OS & verify that
bit 22 of CIR31C register is set. s0ix works.

Change-Id: Ide2d01536f652cd1b0ac32eede89ec410c5101cf
Signed-off-by: Naresh G Solanki 
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pmc.h
2 files changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/19442/7