Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60944 )
Change subject: soc/intel/tgl/pcie_rp: add TGL-H support
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Patch Set 4:
(1 comment)
File src/soc/intel/tigerlake/pcie_rp.c:
https://review.coreboot.org/c/coreboot/+/60944/comment/626b7bca_6d869721
PS1, Line 24: { .slot = SA_DEV_SLOT_CPU_PCIE, .start = 0, .count = 1 },
I can confirm that for TBT ports, it does coalesce them. […]
Huh? I only see coalescing for the CPU ports, not for TBT... doesn't even make any sense, since there is a UPD for CPU ports but not for TBT
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