Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu.
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85505?usp=email )
Change subject: soc/intel/xeon_sp: Introduce early_pch_init ......................................................................
soc/intel/xeon_sp: Introduce early_pch_init
Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage hook and introduce early_pch_init() to do PCH init in romstage before FSP-M runs.
Move PCH specific code into early_pch_init and call it from common code.
Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ebg/soc_pch.c M src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ibl/soc_pch.c M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/romstage.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 10 files changed, 29 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85505/1
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 82657f9..25dc4f6 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -10,7 +10,6 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> -#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include <string.h> @@ -108,10 +107,6 @@
/* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); - - /* FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); }
uint32_t get_max_capacity_mib(void) diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h index acb1785..2b5ed25 100644 --- a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h @@ -3,7 +3,8 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_
+void early_pch_init(void); + void pch_lock_dmictl(void); -void pch_disable_hda(void);
#endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/ebg/soc_pch.c b/src/soc/intel/xeon_sp/ebg/soc_pch.c index a40af7a..3d50fc3 100644 --- a/src/soc/intel/xeon_sp/ebg/soc_pch.c +++ b/src/soc/intel/xeon_sp/ebg/soc_pch.c @@ -10,6 +10,7 @@ #include <soc/azalia_device.h> #include <soc/bootblock.h> #include <soc/soc_pch.h> +#include <soc/pch_pci_devs.h> #include <soc/pch.h> #include <soc/pmc.h> #include <console/console.h> @@ -67,7 +68,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) #define PSF3_HDA_BASE_ADDRESS 0x280
-void pch_disable_hda(void) +static void pch_disable_hda(void) { /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | @@ -82,3 +83,10 @@
printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); } + +void early_pch_init(void) +{ + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h index acb1785..00f0a1b 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h @@ -3,7 +3,7 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_
+void early_pch_init(void); void pch_lock_dmictl(void); -void pch_disable_hda(void);
#endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c index 6bfa749..2bb247c 100644 --- a/src/soc/intel/xeon_sp/ibl/soc_pch.c +++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c @@ -44,3 +44,7 @@ */ soc_config_acpibase(); } + +void early_pch_init(void) +{ +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h index acb1785..2b5ed25 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -3,7 +3,8 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_
+void early_pch_init(void); + void pch_lock_dmictl(void); -void pch_disable_hda(void);
#endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c index 8bc01f7..2eacb4f 100644 --- a/src/soc/intel/xeon_sp/lbg/soc_pch.c +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -64,7 +64,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) #define PSF3_HDA_BASE_ADDRESS 0x1800
-void pch_disable_hda(void) +static void pch_disable_hda(void) { /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | @@ -82,3 +82,10 @@
printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); } + +void early_pch_init(void) +{ + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); +} \ No newline at end of file diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 30bbad7..024dfa5 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -8,11 +8,14 @@ #include <soc/ddr.h> #include <soc/intel/common/smbios.h> #include <soc/romstage.h> +#include <soc/soc_pch.h> #include <soc/util.h> #include <spd.h>
void mainboard_romstage_entry(void) { + early_pch_init(); + rtc_init(); if (soc_get_rtc_failed()) mainboard_rtc_failed(); diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index 819fcc8..f5a4294 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/romstage.h> -#include <device/pci_def.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> -#include <soc/pch_pci_devs.h> -#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include "chip.h" @@ -26,10 +23,6 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; - - /* FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); }
uint8_t get_error_correction_type(const uint8_t RasModesEnabled) diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 4438a59..43eb187 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -17,7 +17,6 @@ #include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> -#include <soc/soc_pch.h> #include <static.h> #include <string.h> #include <soc/config.h> @@ -245,10 +244,6 @@ } if (CONFIG(MEM_POR_FREQ)) mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; - - /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); }
uint8_t get_error_correction_type(const uint8_t RasModesEnabled)
-
Patrick Rudolph (Code Review)