Change in coreboot[master]: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43859 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/ gpio.h
./intelp2m -iiii -n -t 1 -file ../../src/mainboard/razer/ blade_stealth_kbl/gpio.h [1]
This is part of the patch set "mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
- 1/3 Decode raw register values - 2/3 Exclude fields for PAD_CFG - 3/3 Convert field macros to PAD_CFG
[1]
Change-Id: If079604ad1f6e93527691bc27465c6a0fe2c95c7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/razer/blade_stealth_kbl/gpio.h 1 file changed, 150 insertions(+), 300 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/43859/1
diff --git a/src/mainboard/razer/blade_stealth_kbl/gpio.h b/src/mainboard/razer/blade_stealth_kbl/gpio.h index e1e23b2..36a6d55 100644 --- a/src/mainboard/razer/blade_stealth_kbl/gpio.h +++ b/src/mainboard/razer/blade_stealth_kbl/gpio.h @@ -11,718 +11,568 @@ /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { /* GPP_A0 - RCIN# DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A1 - LAD0 DW0: 0x44000702, DW1: 0x00003c00 */ - /* PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
/* GPP_A2 - LAD1 DW0: 0x44000702, DW1: 0x00003c00 */ - /* PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
/* GPP_A3 - LAD2 DW0: 0x44000702, DW1: 0x00003c00 */ - /* PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
/* GPP_A4 - LAD3 DW0: 0x44000702, DW1: 0x00003c00 */ - /* PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)),
/* GPP_A5 - LFRAME# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A6 - SERIRQ DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A7 - GPIO DW0: 0x84000102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_A7, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, PLTRST, OFF, ACPI),
/* GPP_A8 - CLKRUN# DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A9 - CLKOUT_LPC0 DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_A10 - CLKOUT_LPC1 DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_A11 - GPIO DW0: 0x40100102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), */ - _PAD_CFG_STRUCT(GPP_A11, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP),
/* GPP_A12 - GPIO DW0: 0x04000201, DW1: 0x00000000 */ - /* PAD_CFG_GPO(GPP_A12, 1, PWROK), */ - _PAD_CFG_STRUCT(GPP_A12, PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + PAD_CFG_GPO(GPP_A12, 1, PWROK),
/* GPP_A13 - SUSWARN# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A14 - SUS_STAT# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A15 - SUS_ACK# DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_A16 - SD_1P8_SEL DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A17 - SD_PWR_EN# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A18 - ISH_GP0 DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A19 - ISH_GP1 DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A20 - ISH_GP2 DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A21 - ISH_GP3 DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_A22 - GPIO DW0: 0x44000201, DW1: 0x00000000 */ - /* PAD_CFG_GPO(GPP_A22, 1, DEEP), */ - _PAD_CFG_STRUCT(GPP_A22, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + PAD_CFG_GPO(GPP_A22, 1, DEEP),
/* GPP_A23 - GPIO DW0: 0x40100102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP), */ - _PAD_CFG_STRUCT(GPP_A23, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_APIC(GPP_A23, NONE, DEEP),
/* GPP_B0 - CORE_VID0 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B1 - CORE_VID1 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B2 - VRALERT# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B3 - GPIO DW0: 0x80100100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), */ - _PAD_CFG_STRUCT(GPP_B3, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
/* GPP_B4 - GPIO DW0: 0x44000201, DW1: 0x00000000 */ - /* PAD_CFG_GPO(GPP_B4, 1, DEEP), */ - _PAD_CFG_STRUCT(GPP_B4, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), + PAD_CFG_GPO(GPP_B4, 1, DEEP),
/* GPP_B5 - SRCCLKREQ0# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B6 - SRCCLKREQ1# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B7 - SRCCLKREQ2# DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B8 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ - /* PAD_NC(GPP_B8, NONE), */ - _PAD_CFG_STRUCT(GPP_B8, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_B8, NONE),
/* GPP_B9 - SRCCLKREQ4# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B10 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ - /* PAD_NC(GPP_B10, NONE), */ - _PAD_CFG_STRUCT(GPP_B10, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_B10, NONE),
/* GPP_B11 - EXT_PWR_GATE# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B12 - SLP_S0# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B13 - PLTRST# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_B14 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ - /* PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), */ - _PAD_CFG_STRUCT(GPP_B14, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP),
/* GPP_B15 - GPIO DW0: 0x44000200, DW1: 0x00000000 */ - /* PAD_CFG_GPO(GPP_B15, 0, DEEP), */ - _PAD_CFG_STRUCT(GPP_B15, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPP_B15, 0, DEEP),
/* GPP_B16 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ - /* PAD_NC(GPP_B16, NONE), */ - _PAD_CFG_STRUCT(GPP_B16, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_B16, NONE),
/* GPP_B17 - GPIO DW0: 0x42880100, DW1: 0x00001000 */ - /* PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT), */ - _PAD_CFG_STRUCT(GPP_B17, PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), + PAD_CFG_GPI_ACPI_SCI(GPP_B17, 20K_PD, DEEP, INVERT),
/* GPP_B18 - GPIO DW0: 0x80880102, DW1: 0x00003000 */ - /* PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT), */ - _PAD_CFG_STRUCT(GPP_B18, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), + PAD_CFG_GPI_SCI(GPP_B18, 20K_PU, PLTRST, LEVEL, INVERT),
/* GPP_B19 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ - /* PAD_NC(GPP_B19, NONE), */ - _PAD_CFG_STRUCT(GPP_B19, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_B19, NONE),
/* GPP_B20 - GSPI1_CLK DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_B21 - GSPI1_MISO DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_B22 - GSPI1_MOSI DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_B23 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ - /* PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), */ - _PAD_CFG_STRUCT(GPP_B23, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP),
/* GPP_C0 - SMBCLK DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C1 - SMBDATA DW0: 0x44000702, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_C2 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ - /* PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), */ - _PAD_CFG_STRUCT(GPP_C2, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP),
/* GPP_C3 - SML0CLK DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C4 - SML0DATA DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C5 - GPIO DW0: 0x40900100, DW1: 0x00001000 */ - /* PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP), */ - _PAD_CFG_STRUCT(GPP_C5, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), + PAD_CFG_GPI_APIC_INVERT(GPP_C5, 20K_PD, DEEP),
/* GPP_C6 - RESERVED */
/* GPP_C7 - RESERVED */
/* GPP_C8 - UART0_RXD DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C9 - UART0_TXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C10 - UART0_RTS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C11 - UART0_CTS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C12 - UART1_RXD DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C13 - UART1_TXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C14 - UART1_RTS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C15 - UART1_CTS# DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C16 - I2C0_SDA DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C17 - I2C0_SCL DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C18 - I2C1_SDA DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C19 - I2C1_SCL DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C20 - UART2_RXD DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C21 - UART2_TXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C22 - UART2_RTS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_C23 - UART2_CTS# DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D0 - SPI1_CS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D1 - SPI1_CLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D2 - SPI1_MISO DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D3 - SPI1_MOSI DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D4 - FLASHTRIG DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D5 - ISH_I2C0_SDA DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D6 - ISH_I2C0_SCL DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D7 - ISH_I2C1_SDA DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D8 - ISH_I2C1_SCL DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D9 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI), */ - _PAD_CFG_STRUCT(GPP_D9, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NONE, DEEP, LEVEL, ACPI),
/* GPP_D10 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI), */ - _PAD_CFG_STRUCT(GPP_D10, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NONE, DEEP, LEVEL, ACPI),
/* GPP_D11 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI), */ - _PAD_CFG_STRUCT(GPP_D11, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NONE, DEEP, LEVEL, ACPI),
/* GPP_D12 - GPIO DW0: 0x40000100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI), */ - _PAD_CFG_STRUCT(GPP_D12, PAD_RESET(DEEP) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NONE, DEEP, LEVEL, ACPI),
/* GPP_D13 - ISH_UART0_RXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D14 - ISH_UART0_TXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D15 - ISH_UART0_RTS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D16 - ISH_UART0_CTS# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D17 - DMIC_CLK1 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D18 - DMIC_DATA1 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D19 - DMIC_CLK0 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D20 - DMIC_DATA0 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D21 - SPI1_IO2 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D22 - SPI1_IO3 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_D23 - I2S_MCLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E0 - GPIO DW0: 0x42880100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT), */ - _PAD_CFG_STRUCT(GPP_E0, PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_ACPI_SCI(GPP_E0, NONE, DEEP, INVERT),
/* GPP_E1 - SATAXPCIE1 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E2 - SATAXPCIE2 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E3 - GPIO DW0: 0x40000000, DW1: 0x00000000 */ - /* PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI), */ - _PAD_CFG_STRUCT(GPP_E3, PAD_RESET(DEEP), 0), + PAD_CFG_GPIO_BIDIRECT(GPP_E3, 0, NONE, DEEP, LEVEL, ACPI),
/* GPP_E4 - SATA_DEVSLP0 DW0: 0x04000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), */ + PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(NF1), 0),
/* GPP_E5 - GPIO DW0: 0x82880102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT), */ - _PAD_CFG_STRUCT(GPP_E5, PAD_RESET(PLTRST) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_ACPI_SCI(GPP_E5, NONE, PLTRST, INVERT),
/* GPP_E6 - GPIO DW0: 0x44000200, DW1: 0x00000000 */ - /* PAD_CFG_GPO(GPP_E6, 0, DEEP), */ - _PAD_CFG_STRUCT(GPP_E6, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPP_E6, 0, DEEP),
/* GPP_E7 - GPIO DW0: 0x80180102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI), */ - _PAD_CFG_STRUCT(GPP_E7, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(IOAPIC) | PAD_IRQ_ROUTE(SCI) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_DUAL_ROUTE(GPP_E7, NONE, PLTRST, LEVEL, NONE, IOAPIC, SCI),
/* GPP_E8 - SATALED# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E9 - GPIO DW0: 0x44000200, DW1: 0x00000000 */ - /* PAD_CFG_GPO(GPP_E9, 0, DEEP), */ - _PAD_CFG_STRUCT(GPP_E9, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + PAD_CFG_GPO(GPP_E9, 0, DEEP),
/* GPP_E10 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ - /* PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP), */ - _PAD_CFG_STRUCT(GPP_E10, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + PAD_CFG_TERM_GPO(GPP_E10, 1, 20K_PD, DEEP),
/* GPP_E11 - GPIO DW0: 0x44000201, DW1: 0x00001000 */ - /* PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP), */ - _PAD_CFG_STRUCT(GPP_E11, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), + PAD_CFG_TERM_GPO(GPP_E11, 1, 20K_PD, DEEP),
/* GPP_E12 - GPIO DW0: 0x44000300, DW1: 0x00000000 */ - /* PAD_NC(GPP_E12, NONE), */ - _PAD_CFG_STRUCT(GPP_E12, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + PAD_NC(GPP_E12, NONE),
/* GPP_E13 - DDPB_HPD0 DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E14 - DDPC_HPD1 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E15 - GPIO DW0: 0x42840102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT), */ - _PAD_CFG_STRUCT(GPP_E15, PAD_RESET(DEEP) | PAD_TRIG(EDGE_SINGLE) | PAD_IRQ_ROUTE(SMI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, INVERT),
/* GPP_E16 - GPIO DW0: 0x80880102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT), */ - _PAD_CFG_STRUCT(GPP_E16, PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, LEVEL, INVERT),
/* GPP_E17 - EDP_HPD DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E18 - DDPB_CTRLCLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E19 - DDPB_CTRLDATA DW0: 0x44000700, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_E20 - DDPC_CTRLCLK DW0: 0x44000702, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_E21 - DDPC_CTRLDATA DW0: 0x44000702, DW1: 0x00001000 */ - /* PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), */ + PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)),
/* GPP_E22 - GPIO DW0: 0x40900100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP), */ - _PAD_CFG_STRUCT(GPP_E22, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_APIC_INVERT(GPP_E22, NONE, DEEP),
/* GPP_E23 - GPIO DW0: 0x84000200, DW1: 0x00001000 */ - /* PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST), */ - _PAD_CFG_STRUCT(GPP_E23, PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(20K_PD)), + PAD_CFG_TERM_GPO(GPP_E23, 0, 20K_PD, PLTRST),
/* GPP_F0 - I2S2_SCLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F1 - I2S2_SFRM DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F2 - I2S2_TXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F3 - I2S2_RXD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F4 - I2C2_SDA DW0: 0x44000700, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), */ + PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F5 - I2C2_SCL DW0: 0x44000702, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), */ + PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F6 - I2C3_SDA DW0: 0x44000702, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), */ + PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F7 - I2C3_SCL DW0: 0x44000702, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), */ + PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F8 - I2C4_SDA DW0: 0x44000702, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), */ + PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F9 - I2C4_SCL DW0: 0x44000702, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), */ + PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F10 - ISH_I2C2_SDA DW0: 0x44000b02, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), */ + PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F11 - ISH_I2C2_SCL DW0: 0x44000b02, DW1: 0x02000000 */ - /* PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), */ + PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8),
/* GPP_F12 - EMMC_CMD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F13 - GPIO DW0: 0x44000102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_F13, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI),
/* GPP_F14 - GPIO DW0: 0x44000102, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_F14, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI),
/* GPP_F15 - GPIO DW0: 0x44000100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_F15, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI),
/* GPP_F16 - EMMC_DATA3 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F17 - EMMC_DATA4 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F18 - EMMC_DATA5 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F19 - EMMC_DATA6 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F20 - EMMC_DATA7 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F21 - EMMC_RCLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F22 - EMMC_CLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_F23 - GPIO DW0: 0x40100100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), */ - _PAD_CFG_STRUCT(GPP_F23, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP),
/* GPP_G0 - SD_CMD DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G1 - SD_DATA0 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G2 - SD_DATA1 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G3 - SD_DATA2 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G4 - SD_DATA3 DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G5 - SD_CD# DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G6 - SD_CLK DW0: 0x44000700, DW1: 0x00000000 */ - /* PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), */ + PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ - _PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0),
/* GPP_G7 - GPIO DW0: 0x44000100, DW1: 0x00000000 */ - /* PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), */ - _PAD_CFG_STRUCT(GPP_G7, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), + PAD_CFG_GPI_TRIG_OWN(GPP_G7, NONE, DEEP, OFF, ACPI), };
#endif
Maxim Polyakov has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43859 )
Change subject: mb/razer/blade_stealth_kbl: 3/3 Convert field macros to PAD_CFG ......................................................................
Abandoned
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Maxim Polyakov (Code Review)