[XS] Change in coreboot[master]: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, John Zhao, Kapil Porwal, Subrata Banik, Tarun, Tarun Tuli, Tim Wawrzynczak, Utkarsh H Patel.

Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, John Zhao, Kapil Porwal, Tarun, Tarun Tuli, Tim Wawrzynczak, Utkarsh H Patel, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84367?usp=email

to look at the new patch set (#2).

Change subject: Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"
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Revert "soc/intel/meteorlake: Skip the TCSS D3 cold entry sequence"

This reverts commit 88a496a9c81ba6447a4c1453a45d09ee79f30309.

This workaround is not valid with the latest Intel PRQ silicon,
so I'm dropping it now. I was able to boot to ChromeOS without any
hang, and I also ran an S0ix cycle without any failures.

BUG=b:244082753
TEST=Able to boot google/rex0 to CrOS.

Change-Id: Idf0da5841705888d2787f61dd6e6fada2fbe3e3e
Signed-off-by: Subrata Banik 
---
M src/soc/intel/meteorlake/acpi/tcss.asl
1 file changed, 1 insertion(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/84367/2