Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s

[Kevin Chang (Code Review)]

Attention is currently required from: Subrata Banik, Peichao Wang, Kane Chen, Tim Wawrzynczak.
Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 )

Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
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Patch Set 7:

(1 comment)

This change is ready for review.

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/62919/comment/ede87e61_273f5908 
PS2, Line 635: s_cfg->PcieRpAspm[i] = config->pcierpaspm[i];
> Hi Kane, […]

Hi Kane and Subrata

I had modify define to new method in latest patch, Is this method acceptable?