Change in coreboot[master]: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't do mmapping but still want to use the cbmem to store the mrc_cache data in order to write the mrc_cache data back at a later time. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time.
BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 15 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/1
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fe0b9a7..acca7fe 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -10,6 +10,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 78cac30..84cfbf0 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -9,6 +9,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 1918428..e5a119b 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -9,6 +9,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 42068f4..644c211 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -42,8 +42,16 @@ Provide common implementation of the RW boot device that doesn't provide mmap() operations.
+config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + bool + default n + depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + For x86 platforms who do not include the boot_device_rw_nommap libraries in romstage + config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY bool + default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES default n depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP help diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8..00e9a3a 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
config CBFS_SIZE hex diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 29ebc6d..fe43a72 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -44,7 +44,6 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index b29bd99..6737c02 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -41,7 +41,6 @@ select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 33acf43..d35ae62 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -10,7 +10,6 @@ select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a30333b..71a17ff 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -25,7 +25,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index b23f56d..90b4e1d 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -12,6 +12,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index bf067da..5c9988c 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -12,6 +12,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 156d58a..c59e0ca 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -12,6 +12,7 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 596de41..f043955 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -78,7 +78,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 91b45dc..ce2e0b4 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -13,7 +13,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index 166bda0..920f231 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1e66e97..6af8fd2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 15dc1b3..e851fbe 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index db0f688..1c8a7c0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -23,7 +23,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d92d496..6917ab9 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -12,7 +12,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 31d12fc..8d87628 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -29,7 +29,6 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 1:
(5 comments)
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@10 PS1, Line 10: don't do mmapping but still want to use the do not allow write to SPI flash when early stages are running XIP from the flash.
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@11 PS1, Line 11: cbmem to store the mrc_cache data in order to write the mrc_cache data : back at a later time Also, if this config is not selected, BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES gets auto-selected which means all future platforms don't need to worry about selecting BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES. This is under the assumption that most platforms going forward would be fine doing writes to SPI flash even in early stages.
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@15 PS1, Line 15: Also, mention that BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY selection is dropped from current platforms as this config is getting auto-selected.
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@18 PS1, Line 18: ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a I think it would be good to check builds for the platforms for which the config change is being made using the timeless option. It will allow you to confirm that there are no functional changes because of this CL.
https://review.coreboot.org/c/coreboot/+/45740/1/src/drivers/spi/Kconfig File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/45740/1/src/drivers/spi/Kconfig@50 PS1, Line 50: For x86 platforms who do not include the boot_device_rw_nommap libraries I think we should say that this config is used by platforms that do not allow writes to SPI flash in early stages. No need to mention x86 here. Also, we should indicate that not selecting this config results in auto-selection of BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP is selected by the platform.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@11 PS1, Line 11: cbmem to store the mrc_cache data in order to write the mrc_cache data : back at a later time
Also, if this config is not selected, BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES gets auto-selected which […]
Do you mean BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY gets autoselected if BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@11 PS1, Line 11: cbmem to store the mrc_cache data in order to write the mrc_cache data : back at a later time
Do you mean BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY gets autoselected if BOOT_DEVICE_SPI_FLASH_NO_EARL […]
Woops yeah. Sorry, bad copy paste :).
Hello build bot (Jenkins), Furquan Shaikh, Damien Zammit, David Guckian, Vanessa Eusebio, Julius Werner, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45740
to look at the new patch set (#2).
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability.
BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 15 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/2
Hello build bot (Jenkins), Furquan Shaikh, Damien Zammit, David Guckian, Vanessa Eusebio, Julius Werner, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45740
to look at the new patch set (#3).
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability.
BUG=b:150502246 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 19 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/3
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@10 PS1, Line 10: don't do mmapping but still want to use the
do not allow write to SPI flash when early stages are running XIP from the flash.
Done
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@11 PS1, Line 11: cbmem to store the mrc_cache data in order to write the mrc_cache data : back at a later time
Woops yeah. Sorry, bad copy paste :).
Done
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@15 PS1, Line 15:
Also, mention that BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY selection is dropped from current platforms […]
Done
https://review.coreboot.org/c/coreboot/+/45740/1/src/drivers/spi/Kconfig File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/45740/1/src/drivers/spi/Kconfig@50 PS1, Line 50: For x86 platforms who do not include the boot_device_rw_nommap libraries
I think we should say that this config is used by platforms that do not allow writes to SPI flash in […]
Done
Hello build bot (Jenkins), Furquan Shaikh, Damien Zammit, David Guckian, Vanessa Eusebio, Julius Werner, Angel Pons, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45740
to look at the new patch set (#4).
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. We are maintaining the use of cbmem for these older platforms because we have no way of validating the earlier write back to mrc_cache at this time. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability.
BUG=b:150502246 BRANCH=None
TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference.
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 19 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/4
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45740/1//COMMIT_MSG@18 PS1, Line 18: ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a
I think it would be good to check builds for the platforms for which the config change is being made […]
Done
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig@56 PS4, Line 56: config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY Do we still need this option? Can't we just replace all mentions of it with !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES?
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig@56 PS4, Line 56: config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
Do we still need this option? Can't we just replace all mentions of it with !BOOT_DEVICE_SPI_FLASH_N […]
I didn't want to completely remove it (yet) because I was worried that I would mess up and break something that I wasn't aware of. Maybe we can do this as a next step?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig@56 PS4, Line 56: config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
I didn't want to completely remove it (yet) because I was worried that I would mess up and break som […]
`grep` is your best friend 😜
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig File src/drivers/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/45740/4/src/drivers/spi/Kconfig@56 PS4, Line 56: config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
`grep` is your best friend 😜
Will be keeping the BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY config for now. I don't want to split out the macro into different stages in the spi/Makefile.inc file right now. Also, Nico is looking into the possibility of removing the BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES/BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY config for older x86 boards: https://review.coreboot.org/c/coreboot/+/44196/8//COMMIT_MSG#19 so we can clean up the config at that point.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 4: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/45740/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45740/4//COMMIT_MSG@11 PS4, Line 11: We are maintaining the use of : cbmem for these older platforms because we have no way of validating : the earlier write back to mrc_cache at this time. This seems a little out of place.
https://review.coreboot.org/c/coreboot/+/45740/4//COMMIT_MSG@24 PS4, Line 24: GOOGLE_NAMI Ideally you should also test a board that selects BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to ensure timeless build looks okay for it too.
Hello build bot (Jenkins), Furquan Shaikh, Damien Zammit, David Guckian, Vanessa Eusebio, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45740
to look at the new patch set (#5).
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability.
BUG=b:150502246 BRANCH=None
TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 19 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/5
Hello build bot (Jenkins), Furquan Shaikh, Damien Zammit, David Guckian, Vanessa Eusebio, Angel Pons, Julius Werner, Andrey Petrov, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45740
to look at the new patch set (#6).
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability.
BUG=b:150502246 BRANCH=None
TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 19 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/45740/6
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 6: Code-Review+2
Shelley Chen has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate older x86 platforms that don't allow writing to SPI flash when early stages are running XIP from flash. If BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected, BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms that write to flash in the earlier stages, assuming that they have that capability.
BUG=b:150502246 BRANCH=None
TEST=diff the coreboot.rom files resulting from running ./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless with and without this change to make sure that there was no difference. Also did this for GOOGLE_CANDY board, which is baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7 Signed-off-by: Shelley Chen shchen@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/drivers/spi/Kconfig M src/northbridge/intel/x4x/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/stoneyridge/Kconfig M src/soc/intel/alderlake/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 19 insertions(+), 12 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index f58fc54..fbfa714 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -7,6 +7,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index e2b2787..04b9e67 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -6,6 +6,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index b7c9895..5098ac7 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -6,6 +6,7 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select MMX select SSE2 select UDELAY_TSC diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 42068f4..dbde3b2 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -42,8 +42,20 @@ Provide common implementation of the RW boot device that doesn't provide mmap() operations.
+config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES + bool + default n + depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP + help + For platforms who do not allow writes to SPI flash in early + stages like romstage. Not selecting this config will result + in the auto-selection of + BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if + BOOT_DEVICE_SPI_FLASH_RW_NOMMAP is selected by the platform. + config BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY bool + default y if BOOT_DEVICE_SPI_FLASH_RW_NOMMAP && !BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES default n depends on BOOT_DEVICE_SPI_FLASH_RW_NOMMAP help diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 27754c8..00e9a3a 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -12,6 +12,7 @@ select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
config CBFS_SIZE hex diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 849e27b..6a5b932 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -44,7 +44,6 @@ select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select PROVIDES_ROM_SHARING select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index a7e79b4..2ef90eb 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -38,7 +38,6 @@ select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP select PARALLEL_MP_AP_WORK select HAVE_SMI_HANDLER diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 553131b..8f12350 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -11,7 +11,6 @@ select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index a39e4bb..da57931 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -22,7 +22,6 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NO_PCAT_8259 select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES # CPU specific options select CPU_INTEL_COMMON diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 12e1959..8276da2 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -9,6 +9,7 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index c40cafd..ae4fc21 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -9,6 +9,7 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 31f47f7..15ece2c 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -9,6 +9,7 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 + select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f792e70..b0335cf 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -75,7 +75,6 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 866d67e..798d473 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select DEBUG_GPIO select SOC_INTEL_COMMON diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index ba04a4f..1a0bfd2 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -9,7 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 60cb5e5..cad3119 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -9,7 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 2282655..53d6e64 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -9,7 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 155df58..6bdb615 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,7 +20,6 @@ select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ACPI_NHLT select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 7e143c1..ac98779 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -9,7 +9,6 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_COMMON diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 3b18741..e449409 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -26,7 +26,6 @@ config CPU_SPECIFIC_OPTIONS def_bool y select ARCH_ALL_STAGES_X86_32 - select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CPU_INTEL_COMMON select SOC_INTEL_COMMON
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45740 )
Change subject: drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config ......................................................................
Patch Set 7:
Automatic boot test returned (PASS/FAIL/TOTAL): 5/1/6 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/21956 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21955 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/21954 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/21953 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/21951 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/21950
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Furquan Shaikh (Code Review)
-
Julius Werner (Code Review)
-
Shelley Chen (Code Review)