[S] Change in coreboot[main]: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+
Attention is currently required from: Ashish Kumar Mishra, Paul Menzel, Sowmya Aralguppe, Subrata Banik, Wonkyu Kim.
Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/83946?usp=email )
Change subject: soc/intel/common/block/cpu: Add Kconfig for effective way size for NEM+ ......................................................................
Patch Set 13:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83946/comment/5cbdb6f7_11c4b308?usp... : PS13, Line 23: The issue addressed by this commit can be observed with the following : experiment: using a 18 MB LLC SKU, set `DCACHE_RAM_SIZE` to : 0x400000 (4 MB).
This isn't a real issue, it's just a hypothesis that CONFIG_DCACHE_RAM_SIZE is larger than the way size.
The coreboot enhanced NEM code allows `CONFIG_DCACHE_RAM_SIZE` requiring multiple ways but it violate the Alder Lake, Meteor Lake and Panther Lake specification if such a configuration is used ⇒ the code is wrong and this is the issue these CL are addressing. These CL address a coreboot Intel eNEM code issue not a Google board issue.
If you believe that `CONFIG_DCACHE_RAM_SIZE` should never be larger than the effective way size, then why does the bootblock eNEM support multiple ways ? And why is violating the specification by not considering the effective way size ?
If you refuse the code to be fixed arguing that no configuration is taking advantage of it, please implement a mechanism in bootblock limiting the configuration to one **effective** way and remove the support for multiple ways. My only objective here is to fix code that does not comply with the specification and I was able to verify the code does not work by tweaking the configuration. *I tweaked the configuration, not the code*.
My experiments demonstrated that 4MB works like a charm only with these two CLs.
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Jérémy Compostella (Code Review)