[M] Change in coreboot[master]: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel.

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74565 )

Change subject: soc/amd/phoenix/include/soc/pci_devs: update defines to match the PPR
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Patch Set 1:

(1 comment)

File src/soc/amd/phoenix/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/74565/comment/3563ce2c_2827dcdd 
PS1, Line 43: PCIE_GPP_2_1_FUNC
> Thanks for making 1 = 1, the 0 = 1 was always very confusing.

the gpp bridge number always was off by one in the ppr; since we now have bridges on both device 1 and device 2, we moved over to using the device and function numbers