Change in coreboot[master]: sb/intel/bd82x6x: Add Awareness of ME's AltDisable

[Nathaniel Roach (Code Review)]

Nathaniel Roach has uploaded this change for review. ( https://review.coreboot.org/21466

Change subject: sb/intel/bd82x6x: Add Awareness of ME's AltDisable
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sb/intel/bd82x6x: Add Awareness of ME's AltDisable

me_cleaner now allows setting a bit in the PCH
straps - AltDisableBit tells the ME to stop
execution after BUP - disabling the 30 minute
watchdog - but also "breaking" the ME. The ME
reports OpMode = 2.

This means the ME will not respond when we wait
for an acknowledgement about the DRAM being ready.

Change the label for OpMode = 2 from DEBUG to
DISABLE, and when DISABLEd, don't wait for a response
to the DRAM notification.

Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa
Signed-off-by: Nathaniel Roach 
---
M src/southbridge/intel/bd82x6x/early_me.c
M src/southbridge/intel/bd82x6x/me.c
M src/southbridge/intel/bd82x6x/me.h
M src/southbridge/intel/bd82x6x/me_8.x.c
4 files changed, 16 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21466/1

diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index b2e9200..48595ee 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -191,18 +191,22 @@
    meDID = did.uma_base | (1 << 28);// | (1 << 23);
    pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);

-	timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
-	udelay(1100);
-
    /* Must wait for ME acknowledgement */
-	millisec = 0;
-	hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
-	while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
-		udelay(1000);
+	if (opmode == ME_HFS_MODE_DISABLED) {
+		printk(BIOS_NOTICE, "ME: ME is reporting as disabled, so not waiting for a response.\n");
+	} else {
+		timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);
+		udelay(1100);
+		millisec = 0;
    	hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
-		millisec++;
+		while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {
+			udelay(1000);
+			hfs = (pci_read_config32(PCI_DEV(0, b617e32bb99af608b7609583815e876d348025ac0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;
+			millisec++;
+		}
+		timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
    }
-	timestamp_add_now(TS_ME_INFORM_DRAM_DONE);
+

me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);
    printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 70ba301..433f864 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -576,7 +576,7 @@
    switch (hfs.operation_mode) {
    case ME_HFS_MODE_NORMAL:
    	break;
-	case ME_HFS_MODE_DEBUG:
+	case ME_HFS_MODE_DISABLED:
    case ME_HFS_MODE_DIS:
    case ME_HFS_MODE_OVER_JMPR:
    case ME_HFS_MODE_OVER_MEI:
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index f95a0b4..39bfabb 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -49,7 +49,7 @@
 #define  ME_HFS_ERROR_IMAGE	3
 #define  ME_HFS_ERROR_DEBUG	4
 #define  ME_HFS_MODE_NORMAL	0
-#define  ME_HFS_MODE_DEBUG	2
+#define  ME_HFS_MODE_DISABLED	2
 #define  ME_HFS_MODE_DIS	3
 #define  ME_HFS_MODE_OVER_JMPR	4
 #define  ME_HFS_MODE_OVER_MEI	5
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 2e29233..5a9b60a 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -556,7 +556,7 @@
    switch (hfs.operation_mode) {
    case ME_HFS_MODE_NORMAL:
    	break;
-	case ME_HFS_MODE_DEBUG:
+	case ME_HFS_MODE_DISABLED:
    case ME_HFS_MODE_DIS:
    case ME_HFS_MODE_OVER_JMPR:
    case ME_HFS_MODE_OVER_MEI: