Change in coreboot[master]: soc/intel/common: Use heci_reset() in the CSE TX and RX flows

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Patrick Rudolph.
Hello build bot (Jenkins), Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/62587

to look at the new patch set (#4).

Change subject: soc/intel/common: Use heci_reset() in the CSE TX and RX flows
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soc/intel/common: Use heci_reset() in the CSE TX and RX flows

The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is a timeout or malformed
response is received from the CSE. Also, the patch triggers HECI
interface reset if the CSE link state is not ready in the heci_send()
API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla 
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62587/4