[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Subrata Banik (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 8:

(2 comments)

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/43bf1b12_dc6d87f1?usp... :
PS7, Line 341: pmc_clear_gpi_gpe0_status
> Okay. let me know if I can remove these two or keep them with the GPE1 support.

I would say, please keep those as TODO item for b/357011633 and we can revisit later

File src/soc/intel/common/block/pmc/pmclib.c:

https://review.coreboot.org/c/coreboot/+/84104/comment/56bf8a5f_20097068?usp... :
PS8, Line 321: 	soc_pmc_disable_std_gpe1(mask);
> The only thing left is that if the EN bit(s) have been set prior to going to suspend.

I had the impression that BIOS can always set EN bit for all GPE0/GPE1 (as part of GPIO programming aka gpi_enable_gpe) and status is what will be handled by HW event.