[L] Change in coreboot[main]: vc/intel/fsp2_0: Add Skeleton FSP header for PTL

[Subrata Banik (Code Review)]

Attention is currently required from: Saurabh Mishra.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83732?usp=email )

Change subject: vc/intel/fsp2_0: Add Skeleton FSP header for PTL
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Patch Set 3: Code-Review+1

(1 comment)

File src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h:

https://review.coreboot.org/c/coreboot/+/83732/comment/035bf6cb_ddfb462d?usp... :
PS3, Line 43: ///
            : /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
            : ///
            : typedef struct {
            :   UINT8             Revision;         ///< Chipset Init Info Revision
            :   UINT8             Rsvd[3];          ///< Reserved
            :   UINT16            MeChipInitCrc;    ///< 16 bit CRC value of MeChipInit Table
            :   UINT16            BiosChipInitCrc;  ///< 16 bit CRC value of PchChipInit Table
            : } CHIPSET_INIT_INFO;
            : 
do we have a consumer for this ?