Attention is currently required from: Cliff Huang, Kapil Porwal, Pranava Y N, Subrata Banik.
Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83798?usp=email )
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage ......................................................................
Patch Set 43:
(9 comments)
File src/soc/intel/pantherlake/chip.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/67d3abcd_de6ee35b?usp... : PS38, Line 139: /* Perform silicon specific init. */
looks like you have skipped tbt_authentication and soc_enable_tracehub entries
Added.
https://review.coreboot.org/c/coreboot/+/83798/comment/df570ae4_4addd15b?usp... : PS38, Line 139: /* Perform silicon specific init. */
looks like you have skipped tbt_authentication and soc_enable_tracehub entries
Added the entries.
File src/soc/intel/pantherlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/84fada37_a3a04bdb?usp... : PS38, Line 78: msr.lo |= (1 << 23); /* Lock it */
wondering why did you overlooked https://review.coreboot. […]
Added.
File src/soc/intel/pantherlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/a5c3071a_44f10506?usp... : PS38, Line 15:
please adopt 64-bit support for Crashlog like Intel added sometime back […]
Updated the crashlog as per MTL implementation & to adopt 64Bit.
https://review.coreboot.org/c/coreboot/+/83798/comment/91334600_b5302e6a?usp... : PS38, Line 59: u32
this has been fixed in past using https://review.coreboot. […]
Updated the crashlog as per MTL implementation.
https://review.coreboot.org/c/coreboot/+/83798/comment/76824980_ea1d7a01?usp... : PS38, Line 59: u32
this has been fixed in past using https://review.coreboot. […]
Updated the crsshlog
File src/soc/intel/pantherlake/include/soc/crashlog.h:
https://review.coreboot.org/c/coreboot/+/83798/comment/b4a7d95e_53a61ae1?usp... : PS38, Line 22:
please follow https://review.coreboot. […]
Adopted the change as per ref. Cl shared.
https://review.coreboot.org/c/coreboot/+/83798/comment/4e516ce5_95e95973?usp... : PS38, Line 22:
please follow https://review.coreboot. […]
Added.
File src/soc/intel/pantherlake/me.c:
https://review.coreboot.org/c/coreboot/+/83798/comment/03ba57cc_9b3c3c54?usp... : PS38, Line 8:
follow https://review.coreboot. […]
Updated, file removed.