Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/52677 )
Change subject: soc/amd/common: Remove eSPI decode workaround ......................................................................
soc/amd/common: Remove eSPI decode workaround
We no longer lock up if we clear the port 80 bit. I'm assuming this was fixed when we configured the PSP to no longer setup eSPI.
BUG=b:183974365 TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I1530d08974d42e0b06eb783521dea32fca752d85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52677 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-by: Martin Roth martinroth@google.com --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 1 insertion(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Marshall Dawson: Looks good to me, approved
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 82f2a85..7752eb5 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -103,11 +103,7 @@ unsigned int idx;
/* First turn off all enable bits, then zero base, range, and size registers */ - /* - * There is currently a bug where the SMU will lock up at times if the port80h enable - * bit is cleared. See b/183974365 - */ - espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); + espi_write16(ESPI_DECODE, 0);
for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { espi_write16(ESPI_IO_RANGE_BASE(idx), 0);