[XS] Change in coreboot[main]: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84236?usp=email )

Change subject: soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways
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soc/intel/cmn/block/cpu: Simplify calculation of non-eviction ways

The calculation of non-eviction ways (used for cache-as-ram
configuration) has been simplified by removing conditional move
instructions and directly adding the remainder to the quotient.

This achieves the same ceiling operation but with potentially improved
efficiency (lesser instructions).

No functional changes are expected.

TEST=Able to build and boot google/rex.

Change-Id: I7cf5ff19ec440d049edc3bf52c660dea96b1f08a
Signed-off-by: Subrata Banik 
---
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
1 file changed, 1 insertion(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/84236/1

diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 90da9e7..9e24589 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -513,12 +513,9 @@
    xor	%edx, %edx /* Clear the upper 32-bit of dividend */
    div	%ecx
    /*
-	 * Increment data_ways by 1 if RW data size (CONFIG_DCACHE_RAM_SIZE) is
+	 * Effectively ceiling the result if RW data size (CONFIG_DCACHE_RAM_SIZE) is
     * not divisible by way_size (ECX)
     */
-	movl	$0x01, %ecx
-	cmp	$0x00, %edx
-	cmovne	%ecx, %edx
    add	%edx, %eax
    mov	%eax, %edx /* back up data_ways in edx */
    mov	%eax, %ecx