the following patch was just integrated into master: commit 1b9635de6613548449cd2689d212cd6f01dbfd54 Author: rsatapat rishavnath.satapathy@intel.com Date: Wed Jun 24 20:49:16 2015 +0530
Skylake: Initialize GPIOs for UART2
FSP will initialize GPIOs during TempRamInit. So configure LPSS UART2 GPIOs in native mode after TempRamInit.
BRANCH=none BUG=chrome-os-partner:41374 EST=Build and boot on RVP3. Check LPSS logs on UART2
Change-Id: I8016dd76a5bc06e90f9460273be7e83c5e8f8bb1 Signed-off-by: Patrick Georgi pgeorgi@chromium.org Original-Commit-Id: eb72e715ef3f566e900727ac8b9494bca1d5971c Original-Change-Id: If1b1a1047ebd5e5f170d91972d11c51aa6fd84a9 Original-Signed-off-by: rsatapat rishavnath.satapathy@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/281604 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Wenkai Du wenkai.du@intel.com Original-Tested-by: Wenkai Du wenkai.du@intel.com Reviewed-on: http://review.coreboot.org/10995 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org
See http://review.coreboot.org/10995 for details.
-gerrit