Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46892 )
Change subject: soc/intel/broadwell: Align PCI device macros with Haswell ......................................................................
soc/intel/broadwell: Align PCI device macros with Haswell
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: I6b4b032ad9901cb39c9b8f3564c06680febbc12c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/finalize.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/broadwell/pch/pch.h M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/broadwell/report_platform.c 12 files changed, 44 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46892/1
diff --git a/src/soc/intel/broadwell/bootblock.c b/src/soc/intel/broadwell/bootblock.c index 3064cd8..fc56e4e 100644 --- a/src/soc/intel/broadwell/bootblock.c +++ b/src/soc/intel/broadwell/bootblock.c @@ -22,7 +22,7 @@ * 4GiB. */ reg = 0; - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } diff --git a/src/soc/intel/broadwell/early_init.c b/src/soc/intel/broadwell/early_init.c index 52955d6..af5ba14 100644 --- a/src/soc/intel/broadwell/early_init.c +++ b/src/soc/intel/broadwell/early_init.c @@ -11,32 +11,32 @@ static void broadwell_setup_bars(void) { /* Set up all hardcoded northbridge BARs */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, DMIBAR, DMI_BASE_ADDRESS | 1); - pci_write_config32(SA_DEV_ROOT, EPBAR, EP_BASE_ADDRESS | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, MCH_BASE_ADDRESS | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, DMI_BASE_ADDRESS | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, EP_BASE_ADDRESS | 1);
MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1; MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1;
/* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(SA_DEV_ROOT, PAM0, 0x30); - pci_write_config8(SA_DEV_ROOT, PAM1, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM2, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM3, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM4, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM5, 0x33); - pci_write_config8(SA_DEV_ROOT, PAM6, 0x33); + pci_write_config8(HOST_BRIDGE, PAM0, 0x30); + pci_write_config8(HOST_BRIDGE, PAM1, 0x33); + pci_write_config8(HOST_BRIDGE, PAM2, 0x33); + pci_write_config8(HOST_BRIDGE, PAM3, 0x33); + pci_write_config8(HOST_BRIDGE, PAM4, 0x33); + pci_write_config8(HOST_BRIDGE, PAM5, 0x33); + pci_write_config8(HOST_BRIDGE, PAM6, 0x33); }
void systemagent_early_init(void) { const bool vtd_capable = - !(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE); + !(pci_read_config32(HOST_BRIDGE, CAPID0_A) & VTD_DISABLE);
broadwell_setup_bars();
/* Device enable: IGD and Mini-HD */ - pci_write_config32(SA_DEV_ROOT, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN); + pci_write_config32(HOST_BRIDGE, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
if (vtd_capable) { /* setup BARs: zeroize top 32 bits; set enable bit */ diff --git a/src/soc/intel/broadwell/haswell.h b/src/soc/intel/broadwell/haswell.h index c15b39a..dfce0fd 100644 --- a/src/soc/intel/broadwell/haswell.h +++ b/src/soc/intel/broadwell/haswell.h @@ -141,7 +141,7 @@ #define SA_DEV_SLOT_ROOT 0x00 #define SA_DEVFN_ROOT PCI_DEVFN(SA_DEV_SLOT_ROOT, 0) #if defined(__SIMPLE_DEVICE__) -#define SA_DEV_ROOT PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) +#define HOST_BRIDGE PCI_DEV(0, SA_DEV_SLOT_ROOT, 0) #endif
#define SA_DEV_SLOT_IGD 0x02 diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index efde641..1409c20 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -19,7 +19,7 @@ * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t dpr = pci_read_config32(HOST_BRIDGE, DPR); uintptr_t tom = ALIGN_DOWN(dpr, 1 * MiB);
/* Subtract DMA Protected Range size if enabled */ @@ -36,8 +36,8 @@
void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg = pci_read_config32(SA_DEV_ROOT, TSEG); - uintptr_t bgsm = pci_read_config32(SA_DEV_ROOT, BGSM); + uintptr_t tseg = pci_read_config32(HOST_BRIDGE, TSEG); + uintptr_t bgsm = pci_read_config32(HOST_BRIDGE, BGSM);
tseg = ALIGN_DOWN(tseg, 1 * MiB); bgsm = ALIGN_DOWN(bgsm, 1 * MiB); diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/soc/intel/broadwell/pch/bootblock.c index db81691..79cfe90 100644 --- a/src/soc/intel/broadwell/pch/bootblock.c +++ b/src/soc/intel/broadwell/pch/bootblock.c @@ -14,7 +14,7 @@
static void map_rcba(void) { - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1); }
static void enable_port80_on_lpc(void) @@ -49,16 +49,16 @@ static void pch_enable_bars(void) { /* Set up southbridge BARs */ - pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, RCBA_BASE_ADDRESS | 1);
- pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, PMBASE, ACPI_BASE_ADDRESS | 1);
- pci_write_config8(PCH_DEV_LPC, ACPI_CNTL, ACPI_EN); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN);
- pci_write_config32(PCH_DEV_LPC, GPIO_BASE, GPIO_BASE_ADDRESS | 1); + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, GPIO_BASE_ADDRESS | 1);
/* Enable GPIO functionality. */ - pci_write_config8(PCH_DEV_LPC, GPIO_CNTL, GPIO_EN); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, GPIO_EN); }
static void pch_early_lpc(void) @@ -66,12 +66,12 @@ pch_enable_bars();
/* Set COM1/COM2 decode range */ - pci_write_config16(PCH_DEV_LPC, LPC_IO_DEC, 0x0010); + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
/* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; - pci_write_config16(PCH_DEV_LPC, LPC_EN, lpc_config); + pci_write_config16(PCH_LPC_DEV, LPC_EN, lpc_config);
/* Enable IOAPIC */ RCBA16(OIC) = 0x0100; diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/soc/intel/broadwell/pch/early_pch.c index b0fd801..4f59397 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/soc/intel/broadwell/pch/early_pch.c @@ -58,10 +58,10 @@
const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
- pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); }
void pch_early_init(void) diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/soc/intel/broadwell/pch/finalize.c index 44d6f53..fea08b2 100644 --- a/src/soc/intel/broadwell/pch/finalize.c +++ b/src/soc/intel/broadwell/pch/finalize.c @@ -27,10 +27,10 @@ RCBA8(FDSW) |= 1 << 7;
/* Global SMI Lock */ - pci_or_config16(PCH_DEV_LPC, GEN_PMCON_1, SMI_LOCK); + pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, SMI_LOCK);
/* GEN_PMCON Lock */ - pci_or_config8(PCH_DEV_LPC, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK); + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK);
/* PMSYNC */ RCBA32_OR(PMSYNC_CONFIG, 1 << 31); diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c index 4b8f3a7..b4315b6 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -14,12 +14,12 @@
u8 pch_revision(void) { - return pci_read_config8(PCH_DEV_LPC, PCI_REVISION_ID); + return pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID); }
u16 pch_type(void) { - return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); + return pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); }
/* Return 1 if PCH type is WildcatPoint */ diff --git a/src/soc/intel/broadwell/pch/pch.h b/src/soc/intel/broadwell/pch/pch.h index cd5dc0f..b143edc 100644 --- a/src/soc/intel/broadwell/pch/pch.h +++ b/src/soc/intel/broadwell/pch/pch.h @@ -74,7 +74,7 @@ #define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 3) #define PCH_DEVFN_SATA2 _PCH_DEVFN(LPC, 5) #define PCH_DEVFN_THERMAL _PCH_DEVFN(LPC, 6) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_LPC_DEV _PCH_DEV(LPC, 0) #define PCH_DEV_IDE _PCH_DEV(LPC, 1) #define PCH_DEV_SATA _PCH_DEV(LPC, 2) #define PCH_DEV_SMBUS _PCH_DEV(LPC, 3) diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index 7390309..bb80550 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -100,9 +100,9 @@ ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2)); ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
- ps->gen_pmcon1 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_1); - ps->gen_pmcon2 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_2); - ps->gen_pmcon3 = pci_read_config16(PCH_DEV_LPC, GEN_PMCON_3); + ps->gen_pmcon1 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_1); + ps->gen_pmcon2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2); + ps->gen_pmcon3 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_3);
ps->prev_sleep_state = prev_sleep_state(ps);
diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c index a4a9b26..270b4d2 100644 --- a/src/soc/intel/broadwell/pch/smihandler.c +++ b/src/soc/intel/broadwell/pch/smihandler.c @@ -198,12 +198,12 @@ /* Always set the flag in case CMOS was changed on runtime. For * "KEEP", switch to "OFF" - KEEP is software emulated */ - reg8 = pci_read_config8(PCH_DEV_LPC, GEN_PMCON_3); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); if (s5pwr == MAINBOARD_POWER_ON) reg8 &= ~1; else reg8 |= 1; - pci_write_config8(PCH_DEV_LPC, GEN_PMCON_3, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */ busmaster_disable_on_bus(0); @@ -416,7 +416,7 @@
// BIOSWR if (tco_sts & (1 << 8)) { - u8 bios_cntl = pci_read_config16(PCH_DEV_LPC, BIOS_CNTL); + u8 bios_cntl = pci_read_config16(PCH_LPC_DEV, BIOS_CNTL);
if (bios_cntl & 1) { /* @@ -430,7 +430,7 @@ * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_DEV_LPC, BIOS_CNTL, (bios_cntl & ~1)); + pci_write_config32(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ diff --git a/src/soc/intel/broadwell/report_platform.c b/src/soc/intel/broadwell/report_platform.c index 205190b..b649ebb 100644 --- a/src/soc/intel/broadwell/report_platform.c +++ b/src/soc/intel/broadwell/report_platform.c @@ -123,8 +123,8 @@ static void report_mch_info(void) { int i; - u16 mch_device = pci_read_config16(SA_DEV_ROOT, PCI_DEVICE_ID); - u8 mch_revision = pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + u16 mch_device = pci_read_config16(HOST_BRIDGE, PCI_DEVICE_ID); + u8 mch_revision = pci_read_config8(HOST_BRIDGE, PCI_REVISION_ID); const char *mch_type = "Unknown";
/* Look for string to match the revision for Broadwell U/Y */
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46892
to look at the new patch set (#7).
Change subject: soc/intel/broadwell: Align PCI device macros with Haswell ......................................................................
soc/intel/broadwell: Align PCI device macros with Haswell
Tested with BUILD_TIMELESS=1, Google Buddy does not change.
Change-Id: I6b4b032ad9901cb39c9b8f3564c06680febbc12c Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/bootblock.c M src/soc/intel/broadwell/early_init.c M src/soc/intel/broadwell/haswell.h M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pch/bootblock.c M src/soc/intel/broadwell/pch/early_pch.c M src/soc/intel/broadwell/pch/finalize.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/broadwell/pch/pch.h M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/broadwell/pch/smihandler.c M src/soc/intel/broadwell/report_platform.c 12 files changed, 44 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/46892/7
-
Angel Pons (Code Review)