Attention is currently required from: Lance Zhao, Anil Kumar K, Selma Bensaid, Tim Wawrzynczak, Paul Menzel, Thejaswani Putta, Patrick Rudolph. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61352 )
Change subject: soc/intel/common/block/pcie/rtd3: Add PM methods to the device. ......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/chip.h:
https://review.coreboot.org/c/coreboot/+/61352/comment/5f0b152f_5350c758 PS1, Line 53: ext_pm_support
Hi Tim, Since this header is not exposed to the device code, I couldn't find a way to inform the device what methods has been exported and available to the device via enum. However, I am adding this table as comments.
/* * Provides L23, modPHY gating, source clock enabling methods to the device * connected root port, mainly used in the device ACPI methods such as reset. * The methods to export are following this table: *-----------------------------------------------------------------------------------* | ext_pm_support | disable_l123 | srcclk_pin | rp_type | exppoted methods | *----------------+--------------+------------+-------------+------------------------* | false | - | - | - | None | | true | true | =0 | PCIE_RP_CPU | None | | true | true | =0 | PCIE_RP_PCH | SRCK | | true | true | >0 | PCIE_RP_CPU | PSD0 | | true | true | >0 | PCIE_RP_PCH | PSD0, SRCK | | true | false | =0 | PCIE_RP_CPU | L23D, LD23 | | true | false | =0 | PCIE_RP_PCH | L23D, LD23, SRCK | | true | false | >0 | PCIE_RP_CPU | L23D, LD23, PSD0 | | true | false | >0 | PCIE_RP_PCH | L23D, LD23, PSD0, SRCK | *-----------------------------------------------------------------------------------* */ Furthermore, CondRefof() will be used in the device code for the methods prior to calling How about it?