[S] Change in coreboot[main]: cpu/x86: Flip order for 1GB page tables to save a bit of space

[Julius Werner (Code Review)]

Attention is currently required from: Jérémy Compostella.

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82793?usp=email )

Change subject: cpu/x86: Flip order for 1GB page tables to save a bit of space
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cpu/x86: Flip order for 1GB page tables to save a bit of space

Linkers are very stupid when it comes to section alignments,
unfortunately. You'd think that when given a wildcard match like
*(.rodata.*) that contains a few small sections with 4K alignment and
many more sections with smaller alignments, they'd be clever enough to
place the 4K sections first and then fill in the gaps between them with
the less restricted sections. Alas, they don't... they'll just generate
a 3.9K NOP sled in front of each section. :( I guess the problem doesn't
come up often enough to be worth optimizing.

Thankfully, they're blindly placing the sections in input order but
they're still able to add in smaller data items after the last
4K-aligned section. For our 1GB page tables that's almost enough,
because we only really have one small 4K-aligned object (PM4LE). So by
reordering things such that that table comes last, we can help the
linker waste a little less space. (There is still some wastage between
the start of .rodata and the first 4K-aligned object which I don't think
we can do anything about. Even if we put them all in separate sections,
they might not be placed at the start of .rodata but they still get
placed randomly in input order without any consideration about how much
alignment adjustment that would require.)

Change-Id: I1c97f504e17d99c77a18c795b4f2b3e59849b5e4
Signed-off-by: Julius Werner 
---
M src/cpu/x86/64bit/pt1G.S
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/82793/1

diff --git a/src/cpu/x86/64bit/pt1G.S b/src/cpu/x86/64bit/pt1G.S
index 3ddb620..0fc6cfd 100644
--- a/src/cpu/x86/64bit/pt1G.S
+++ b/src/cpu/x86/64bit/pt1G.S
@@ -17,13 +17,13 @@
 #define _GEN_DIR(a) (_PRES + _RW + _US + _A + (a))
 #define _GEN_PAGE(a) (_PRES + _RW + _US + _PS + _A +  _D + (a))

-.global PM4LE
-.align 4096
-PM4LE:
-.quad _GEN_DIR(PDE_table)
-
 .align 4096
 PDE_table: /* identity map 1GiB pages * 512 */
 .rept 512
 .quad _GEN_PAGE(0x40000000 * ((. - PDE_table) >> 3))
 .endr
+
+.global PM4LE
+.align 4096
+PM4LE:
+.quad _GEN_DIR(PDE_table)