Attention is currently required from: Angel Pons.
Nico Huber has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/82769?usp=email )
Change subject: nb/via/cx700: Implement FSB tuning ......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/via/cx700/romstage.c:
https://review.coreboot.org/c/coreboot/+/82769/comment/76ce391a_040d81d2?usp... : PS2, Line 47: pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01);
Wasn't there one of these in bootblock? Or does it need to be done again?
There's one in `clock.c`, however that depends on early usage of the timer framework. I don't know but could imagine that it doesn't run with the bootblock console disabled. Also wasn't sure if putting it into soc_early_bootblock_init() (instead of `clock.c`) would be early enough. Just doing it here, potentially again, seemed safest.
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Nico Huber (Code Review)