New subject: Change in coreboot[master]: soc/intel/xeon_sp/cpx: display UPDs and CPX-SP specific HOBs

13 May 2020

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41348 )
Change subject: soc/intel/xeon_sp/cpx: display platform specific HOBs
......................................................................
soc/intel/xeon_sp/cpx: display platform specific HOBs
Add code to support display of platform specific HOBs, and display
of UPD.
Call the hob display functions at chip_start(), instead of using
CONFIG_DISPLAY_HOBS. Otherwise the platform specific HOBs get
displayed hundreds of times; in other words, there is a bug in
CONFIG_DISPLAY_HOBS support code to be solved.
Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77
---
M src/soc/intel/xeon_sp/cpx/Makefile.inc
M src/soc/intel/xeon_sp/cpx/chip.c
A src/soc/intel/xeon_sp/cpx/hob_display.c
A src/soc/intel/xeon_sp/cpx/upd_display.c
4 files changed, 285 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/41348/1

diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc
index 8e300e8..87aad3b 100644
--- a/src/soc/intel/xeon_sp/cpx/Makefile.inc
+++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc
@@ -13,7 +13,11 @@
 subdirs-y += ../../../../cpu/intel/microcode
romstage-y += romstage.c
+romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
+
 ramstage-y += chip.c acpi.c cpu.c soc_util.c
+ramstage-y += hob_display.c
+ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/cpx/include -I$(src)/soc/intel/xeon_sp/cpx
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index 8597a2d..f0eb7b1 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -590,6 +590,9 @@
    printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n");
    fsp_silicon_init(false);
+	soc_display_memmap_hob();
+	soc_display_iio_universal_data_hob();
+
    pch_enable_ioapic(NULL);
    setup_lapic();
    p2sb_unhide();
diff --git a/src/soc/intel/xeon_sp/cpx/hob_display.c b/src/soc/intel/xeon_sp/cpx/hob_display.c
new file mode 100644
index 0000000..424f460
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/hob_display.c
@@ -0,0 +1,200 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+#include <assert.h>
+#include <hob_iiouds.h>
+#include <hob_memmap.h>
+#include <soc/soc_util.h>
+
+static const uint8_t fsp_hob_iio_uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
+static const uint8_t fsp_hob_memmap_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
+
+struct guid_name_map {
+	const void *guid;
+	const char *name;
+};
+
+static const struct guid_name_map  guid_names[] = {
+	{ fsp_hob_iio_uds_guid, "FSP_HOB_IIO_UNIVERSAL_DATA_GUID" },
+	{ fsp_hob_memmap_guid, "FSP_SYSTEM_MEMORYMAP_HOB_GUID" },
+};
+
+const char *soc_get_guid_name(const uint8_t *guid)
+{
+	size_t index;
+
+	/* Compare the GUID values in this module */
+	for (index = 0; index < ARRAY_SIZE(guid_names); index++)
+		if (fsp_guid_compare(guid, guid_names[index].guid))
+			return guid_names[index].name;
+
+	return NULL;
+}
+
+void soc_display_hob(const struct hob_header *hob)
+{
+	const struct hob_resource *res;
+
+	res = fsp_hob_header_to_resource(hob);
+	assert(res != NULL);
+	printk(BIOS_DEBUG, "\tResource type: 0x%x, attribute: 0x%x, addr: 0x%08llx, len: 0x%08llx\n",
+		res->type, res->attribute_type, res->addr, res->length);
+	printk(BIOS_DEBUG, "\tOwner GUID: ");
+	fsp_print_guid(res->owner_guid);
+	printk(BIOS_DEBUG, " (%s)\n", fsp_get_guid_name(res->owner_guid));
+
+	if (fsp_guid_compare(res->owner_guid, fsp_hob_iio_uds_guid) == 0)
+		soc_display_iio_universal_data_hob();
+	else if (fsp_guid_compare(res->owner_guid, fsp_hob_memmap_guid) == 0)
+		soc_display_memmap_hob();
+	else
+		hexdump(hob, hob->length);
+}
+
+void soc_display_memmap_hob(void)
+{
+	size_t hob_size;
+	const struct SystemMemoryMapHob *hob;
+	const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID;
+
+	hob = (const struct SystemMemoryMapHob *)fsp_find_extension_hob_by_guid(
+		mem_hob_guid, &hob_size);
+	assert(hob != NULL);
+
+	printk(BIOS_DEBUG, "===================== MEMORY MAP HOB DATA =====================\n");
+	printk(BIOS_DEBUG, "hob: %p\n", hob);
+	printk(BIOS_DEBUG, "\tlowMemBase: 0x%x, lowMemSize: 0x%x, highMemBase: 0x%x, "
+		"highMemSize: 0x%x\n",
+		hob->lowMemBase, hob->lowMemSize, hob->highMemBase, hob->highMemSize);
+	printk(BIOS_DEBUG, "\tmemSize: 0x%x, memFreq: 0x%x\n",
+		hob->memSize, hob->memFreq);
+
+	printk(BIOS_DEBUG, "\tSystemMemoryMapElement Entries: %d\n", hob->numberEntries);
+	for (int e = 0; e < hob->numberEntries; ++e) {
+		const struct SystemMemoryMapElement *mem_element = &hob->Element[e];
+		printk(BIOS_DEBUG, "\t\tmemory_map %d BaseAddress: 0x%x, ElementSize: 0x%x, Type: 0x%x\n",
+			e, mem_element->BaseAddress,
+			mem_element->ElementSize, mem_element->Type);
+	}
+}
+
+void soc_display_iio_universal_data_hob(void)
+{
+	size_t hob_size;
+	const IIO_UDS *hob;
+	const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID;
+
+	hob = (const IIO_UDS *)fsp_find_extension_hob_by_guid(
+		fsp_hob_iio_universal_data_guid, &hob_size);
+	assert(hob != NULL);
+
+	printk(BIOS_DEBUG, "===================== IIO_UDS HOB DATA =====================\n");
+
+	printk(BIOS_DEBUG, "\t===================== SYSTEM STATUS =====================\n");
+	printk(BIOS_DEBUG, "\tnumCpus: 0x%x\n", hob->SystemStatus.numCpus);
+	printk(BIOS_DEBUG, "\ttolmLimit: 0x%x\n", hob->SystemStatus.tolmLimit);
+	printk(BIOS_DEBUG, "\ttohmLimit: 0x%x\n", hob->SystemStatus.tohmLimit);
+
+	printk(BIOS_DEBUG, "\t===================== PLATFORM DATA =====================\n");
+	printk(BIOS_DEBUG, "\tPlatGlobalIoBase: 0x%x\n", hob->PlatformData.PlatGlobalIoBase);
+	printk(BIOS_DEBUG, "\tPlatGlobalIoLimit: 0x%x\n", hob->PlatformData.PlatGlobalIoLimit);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmiolBase: 0x%x\n",
+		hob->PlatformData.PlatGlobalMmiolBase);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmiolLimit: 0x%x\n",
+		hob->PlatformData.PlatGlobalMmiolLimit);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmiohBase: 0x%llx\n",
+		hob->PlatformData.PlatGlobalMmiohBase);
+	printk(BIOS_DEBUG, "\tPlatGlobalMmiohLimit: 0x%llx\n",
+		hob->PlatformData.PlatGlobalMmiohLimit);
+	printk(BIOS_DEBUG, "\tMemTsegSize: 0x%x\n", hob->PlatformData.MemTsegSize);
+	printk(BIOS_DEBUG, "\tMemIedSize: 0x%x\n", hob->PlatformData.MemIedSize);
+	printk(BIOS_DEBUG, "\tPciExpressBase: 0x%llx\n", hob->PlatformData.PciExpressBase);
+	printk(BIOS_DEBUG, "\tPciExpressSize: 0x%x\n", hob->PlatformData.PciExpressSize);
+	printk(BIOS_DEBUG, "\tMemTolm: 0x%x\n", hob->PlatformData.MemTolm);
+	printk(BIOS_DEBUG, "\tnumofIIO: 0x%x\n", hob->PlatformData.numofIIO);
+	printk(BIOS_DEBUG, "\tMaxBusNumber: 0x%x\n", hob->PlatformData.MaxBusNumber);
+	printk(BIOS_DEBUG, "\tIoGranularity: 0x%x\n", hob->PlatformData.IoGranularity);
+	printk(BIOS_DEBUG, "\tMmiolGranularity: 0x%x\n", hob->PlatformData.MmiolGranularity);
+	printk(BIOS_DEBUG, "\tMmiohGranularity: hi: 0x%x, lo:0x%x\n",
+		hob->PlatformData.MmiohGranularity.hi, hob->PlatformData.MmiohGranularity.lo);
+	printk(BIOS_DEBUG, "\tPci64BitResourceAllocation: 0x%d\n",
+		hob->PlatformData.Pci64BitResourceAllocation);
+
+	for (int s = 0; s < hob->PlatformData.numofIIO; ++s) {
+		printk(BIOS_DEBUG, "\t============ Socket %d Info ================\n", s);
+		printk(BIOS_DEBUG, "\tValid: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].Valid);
+		printk(BIOS_DEBUG, "\tSocketID: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].SocketID);
+		printk(BIOS_DEBUG, "\tBusBase: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].BusBase);
+		printk(BIOS_DEBUG, "\tBusLimit: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].BusLimit);
+		printk(BIOS_DEBUG, "\tPciResourceIoBase: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].PciResourceIoBase);
+		printk(BIOS_DEBUG, "\tPciResourceIoLimit: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].PciResourceIoLimit);
+		printk(BIOS_DEBUG, "\tIoApicBase: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].IoApicBase);
+		printk(BIOS_DEBUG, "\tIoApicLimit: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].IoApicLimit);
+		printk(BIOS_DEBUG, "\tPciResourceMem32Base: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].PciResourceMem32Base);
+		printk(BIOS_DEBUG, "\tPciResourceMem32Limit: 0x%x\n",
+			hob->PlatformData.IIO_resource[s].PciResourceMem32Limit);
+		printk(BIOS_DEBUG, "\tPciResourceMem64Base: 0x%llx\n",
+			hob->PlatformData.IIO_resource[s].PciResourceMem64Base);
+		printk(BIOS_DEBUG, "\tPciResourceMem64Limit: 0x%llx\n",
+			hob->PlatformData.IIO_resource[s].PciResourceMem64Limit);
+
+		printk(BIOS_DEBUG, "\t============ Stack Info ================\n");
+		for (int x = 0; x < MAX_LOGIC_IIO_STACK; ++x) {
+			const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x];
+			printk(BIOS_DEBUG, "\t\t========== Stack %d ===============\n", x);
+			printk(BIOS_DEBUG, "\t\tPersonality: 0x%x\n", ri->Personality);
+			printk(BIOS_DEBUG, "\t\tBusBase: 0x%x\n", ri->BusBase);
+			printk(BIOS_DEBUG, "\t\tBusLimit: 0x%x\n", ri->BusLimit);
+			printk(BIOS_DEBUG, "\t\tPciResourceIoBase: 0x%x\n",
+				ri->PciResourceIoBase);
+			printk(BIOS_DEBUG, "\t\tPciResourceIoLimit: 0x%x\n",
+				ri->PciResourceIoLimit);
+			printk(BIOS_DEBUG, "\t\tIoApicBase: 0x%x\n", ri->IoApicBase);
+			printk(BIOS_DEBUG, "\t\tIoApicLimit: 0x%x\n", ri->IoApicLimit);
+			printk(BIOS_DEBUG, "\t\tPciResourceMem32Base: 0x%x\n",
+				ri->PciResourceMem32Base);
+			printk(BIOS_DEBUG, "\t\tPciResourceMem32Limit: 0x%x\n",
+				ri->PciResourceMem32Limit);
+			printk(BIOS_DEBUG, "\t\tPciResourceMem64Base: 0x%llx\n",
+				ri->PciResourceMem64Base);
+			printk(BIOS_DEBUG, "\t\tPciResourceMem64Limit: 0x%llx\n",
+				ri->PciResourceMem64Limit);
+			printk(BIOS_DEBUG, "\t\tVtdBarAddress: 0x%x\n", ri->VtdBarAddress);
+		}
+
+		printk(BIOS_DEBUG, "\t============ PcieInfo ================\n");
+		IIO_RESOURCE_INSTANCE iio_resource =
+			hob->PlatformData.IIO_resource[s];
+		for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) {
+			printk(BIOS_DEBUG, "\t\tPort: %d, Device: 0x%x, Function: 0x%x\n",
+				p, iio_resource.PcieInfo.PortInfo[p].Device,
+				iio_resource.PcieInfo.PortInfo[p].Function);
+		}
+	}
+}
diff --git a/src/soc/intel/xeon_sp/cpx/upd_display.c b/src/soc/intel/xeon_sp/cpx/upd_display.c
new file mode 100644
index 0000000..f3f78fc
--- /dev/null
+++ b/src/soc/intel/xeon_sp/cpx/upd_display.c
@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 - 2020 Intel Corporation
+ * Copyright (C) 2019 - 2020 Facebook Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+
+#include <console/console.h>
+#include <fsp/util.h>
+#include <lib.h>
+
+#define DUMP_UPD(old, new, field) \
+	fsp_display_upd_value(#field, sizeof(old->field), old->field, new->field)
+
+/* Display the UPD parameters for MemoryInit */
+void soc_display_fspm_upd_params(
+	const FSPM_UPD *fspm_old_upd,
+	const FSPM_UPD *fspm_new_upd)
+{
+	const FSP_M_CONFIG *new;
+	const FSP_M_CONFIG *old;
+
+	old = &fspm_old_upd->FspmConfig;
+	new = &fspm_new_upd->FspmConfig;
+
+	printk(BIOS_DEBUG, "UPD values for MemoryInit:\n");
+
+	DUMP_UPD(old, new, DebugPrintLevel);
+
+	hexdump(fspm_new_upd, sizeof(*fspm_new_upd));
+}
+
+/* Display the UPD parameters for SiliconInit */
+void soc_display_fsps_upd_params(
+	const FSPS_UPD *fsps_old_upd,
+	const FSPS_UPD *fsps_new_upd)
+{
+	const FSPS_CONFIG *new;
+	const FSPS_CONFIG *old;
+
+	old = &fsps_old_upd->FspsConfig;
+	new = &fsps_new_upd->FspsConfig;
+
+	printk(BIOS_DEBUG, "UPD values for SiliconInit:\n");
+
+	DUMP_UPD(old, new, BifurcationPcie0);
+	DUMP_UPD(old, new, BifurcationPcie1);
+	DUMP_UPD(old, new, ActiveCoreCount);
+	DUMP_UPD(old, new, CpuMicrocodePatchBase);
+	DUMP_UPD(old, new, CpuMicrocodePatchSize);
+	DUMP_UPD(old, new, EnablePcie0);
+	DUMP_UPD(old, new, EnablePcie1);
+	DUMP_UPD(old, new, EnableEmmc);
+	DUMP_UPD(old, new, EnableGbE);
+	DUMP_UPD(old, new, FiaMuxConfigRequestPtr);
+	DUMP_UPD(old, new, PcieRootPort0DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort1DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort2DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort3DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort4DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort5DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort6DeEmphasis);
+	DUMP_UPD(old, new, PcieRootPort7DeEmphasis);
+	DUMP_UPD(old, new, EMMCDLLConfigPtr);
+
+	hexdump(fsps_new_upd, sizeof(*fsps_new_upd));
+}
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I42dd519103cc604d4cfee858f4774bd73c979e77
Gerrit-Change-Number: 41348
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Zhang jonzhang@fb.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: soc/intel/xeon_sp/cpx: display platform specific HOBs